VHDL help; signal in architecture?

Discussion in 'Homework Help' started by El3, Nov 28, 2014.

  1. El3

    Thread Starter Member

    Sep 13, 2014
    37
    0
    When writing VHDL code, we first have the entity where all input and output signals are declared. But then in the architecture, what signals are needed to be declared there? I mean isn't it enough that the signals are declared in the entity, why does some signals need to be declared in the architecture?

    For example in the following (unfinished) code, 3 input signals and one output signal are declared in the entity. But then in the architecture there is something called "signal". Why is this necessary?

    Why can't we just use the signals that have already been declared in entity?

    Code (Text):
    1. library ieee;
    2. use ieee.std_logic_1164.all;
    3. use ieee.numeric_std.all;
    4.  
    5. entity edge_det is
    6.  
    7.   port (
    8.     clk, n_rst : in  std_logic;
    9.     inp        : in  std_logic;
    10.     det_edge   : out std_logic);
    11.  
    12. end entity edge_det;
    13.  
    14. architecture edge_det_arch of edge_det is
    15.  
    16.   signal reg_q : std_logic;
    17.  
    18. begin  -- architecture edge_det_arch
    19.  
    20.   -- purpose: register
    21.   -- type   : sequential
    22.   -- inputs : clk, n_rst, reg_in
    23.   -- outputs: reg_q
    24.   reg : process (clk, n_rst) is
    25.   begin
    26.   -----------------------------------------------------------------------------
    27.   -- TODO:
    28.   -- Implement register if necesssary
    29.   -----------------------------------------------------------------------------
    30.   end process reg;
    31.  
    32.   -----------------------------------------------------------------------------
    33.   -- TODO:
    34.   -- Implement the combinational logic to detect the rising edge as drawn in
    35.   -- the home exercise
    36.   -----------------------------------------------------------------------------
    37.  
    38. end architecture edge_det_arch;
    39.  
     
  2. El3

    Thread Starter Member

    Sep 13, 2014
    37
    0
    Is there noone here who've worked with VHDL, who could answer this?
     
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