When writing VHDL code, we first have the entity where all input and output signals are declared. But then in the architecture, what signals are needed to be declared there? I mean isn't it enough that the signals are declared in the entity, why does some signals need to be declared in the architecture?

For example in the following (unfinished) code, 3 input signals and one output signal are declared in the entity. But then in the architecture there is something called "signal". Why is this necessary?

Why can't we just use the signals that have already been declared in entity?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity edge_det is

  port (
    clk, n_rst : in  std_logic;
    inp        : in  std_logic;
    det_edge   : out std_logic);

end entity edge_det;

architecture edge_det_arch of edge_det is

  signal reg_q : std_logic;

begin  -- architecture edge_det_arch

  -- purpose: register
  -- type   : sequential
  -- inputs : clk, n_rst, reg_in
  -- outputs: reg_q
  reg : process (clk, n_rst) is
  begin
  -----------------------------------------------------------------------------
  -- TODO:
  -- Implement register if necesssary
  -----------------------------------------------------------------------------
  end process reg;

  -----------------------------------------------------------------------------
  -- TODO:
  -- Implement the combinational logic to detect the rising edge as drawn in
  -- the home exercise
  -----------------------------------------------------------------------------

end architecture edge_det_arch;

 

Is there noone here who've worked with VHDL, who could answer this?