VHDL help: approximate sigmoid function

Discussion in 'Programmer's Corner' started by ythu, May 13, 2009.

  1. ythu

    Thread Starter New Member

    May 13, 2009
    1
    0
    Hi dear all,
    I m trying to wirte a VHDL code to approximate a simgmoid function. so far I have only get the positive values working properly, but the negative side outputs wierd plot once I use signed value.

    my code is given below. help is appreciated coz I m doing this for a important project.
    thanks in advance.

    library IEEE;
    use IEEE.std_logic_1164.all;
    use ieee.std_logic_signed.all;
    use ieee.std_logic_unsigned.all;
    use IEEE.NUMERIC_STD.ALL;

    entity Dsigmoid is
    port (sigin: in std_logic_vector(16 downto 0);
    sigout: out std_logic_vector(16 downto 0)
    );
    end Dsigmoid;

    architecture DsigTf of Dsigmoid is
    signal temp: integer range -511 to 511;
    signal A1:integer range -511 to 511;
    signal B1: integer range -511 to 511;
    signal vTheta:integer range -65535 to 65535
    signal vv: integer range -262144 to 262144;--std_logic_vector(16 downto 0)
    constant L: integer range -255 to 255:=255;
    constant M: integer range -1023 to 1023:=511;
    begin
    A1<=to_integer(signed(sigin));
    B1<=M+A1 when A1<0 and A1>-L else M-A1;
    vv<=B1*A1;
    vTheta<=vv/256;
    temp<=vTheta;

    sigout<=std_logic_vector(to_unsigned(temp,17)) when A1<L and A1>0
    else std_logic_vector(to_unsigned(temp,17)) when A1<0 and A1>-L
    else std_logic_vector(to_unsigned(L,17)) when A1>=L
    else std_logic_vector(to_unsigned(0,17));
    end DsigTf
     
  2. pscet

    New Member

    Jan 20, 2010
    1
    0
    pls send the sigmoid code to me.I am also doing a project related to that
     
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