Let me start off by saying that I'm brand new to VHDL and I'm trying my best to wrap my head around it. That being said, I'm trying to write a program for the VHDL class I'm taking in school and am having a problem with the statement:
clocking: block(CLK = '0' and not CLK'STABLE)
begin
----code to be inserted----
end block clocking;
When I check the syntax (I'm using Xilinx ISE btw) I get an error on the first line listed above with the error "Guarded signal unsupported in block statement." I don't have anything fancy going on, I just created a new project that contains CLK as an input. This is really the only code that's been written so far as I want to get past this error before moving foward.
Why is it that I'm getting this error? I've taken the examples directly out of the textbook and some samples I've found online. I can't get beyond this error. Any help at all would be greatly appreciated.
Thanks!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity project1_df is
Port ( X : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
Z : out STD_LOGIC);
end project1_df;
architecture DATAFLOW of project1_df is
signal STATE: std_logic_vector (2 downto 0);
begin
clocking: block(CLK = '0' and not CLK'STABLE)
begin
end block clocking;
end DATAFLOW;
clocking: block(CLK = '0' and not CLK'STABLE)
begin
----code to be inserted----
end block clocking;
When I check the syntax (I'm using Xilinx ISE btw) I get an error on the first line listed above with the error "Guarded signal unsupported in block statement." I don't have anything fancy going on, I just created a new project that contains CLK as an input. This is really the only code that's been written so far as I want to get past this error before moving foward.
Why is it that I'm getting this error? I've taken the examples directly out of the textbook and some samples I've found online. I can't get beyond this error. Any help at all would be greatly appreciated.
Thanks!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity project1_df is
Port ( X : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
Z : out STD_LOGIC);
end project1_df;
architecture DATAFLOW of project1_df is
signal STATE: std_logic_vector (2 downto 0);
begin
clocking: block(CLK = '0' and not CLK'STABLE)
begin
end block clocking;
end DATAFLOW;
