1. Rockyy

    Thread Starter New Member

    Jul 10, 2014
    7
    0
    Hello

    I have written a small program in vhdl for practice purpose but i am getting some error like below.Not able to solve the problem

    Parsing architecture <Behavioral> of entity <test1>.
    ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 40: Syntax error near "process".
    ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 42: Syntax error near "then".
    ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 44: Syntax error near "if".
    VHDL file D:\Others\Project\XilingProgramm\test1\test1.vhd ignored due to errors
    Code ( (Unknown Language)):
    1.  
    2. library IEEE;
    3. use IEEE.STD_LOGIC_1164.ALL;
    4.  
    5. entity test1 is
    6.     Port ( clk : in  STD_LOGIC;
    7.            input1 : in  STD_LOGIC;
    8.            input2 : in  STD_LOGIC;
    9.            output : out  STD_LOGIC);
    10. end test1;
    11.  
    12. architecture Behavioral of test1 is
    13.   process(clk)
    14. begin
    15.       if (clk'event and clk='1') then
    16.         output <= input1 and input2;
    17.         end if;
    18. end process;
    19.  
    20. end Behavioral;
    21.  
     
  2. bertus

    Administrator

    Apr 5, 2008
    15,645
    2,344
    Last edited: Aug 8, 2014
  3. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    put the word "begin" between your architecture declaration and the process block.
     
    Rockyy likes this.
  4. Rockyy

    Thread Starter New Member

    Jul 10, 2014
    7
    0
    For the above Program I have created a VHDL test bench like below

    Code ( (Unknown Language)):
    1.  
    2. LIBRARY ieee;
    3. USE ieee.std_logic_1164.ALL;
    4.  
    5. -- Uncomment the following library declaration if using
    6. -- arithmetic functions with Signed or Unsigned values
    7. --USE ieee.numeric_std.ALL;
    8.  
    9. ENTITY test IS
    10. END test;
    11.  
    12. ARCHITECTURE behavior OF test IS
    13.  
    14.     -- Component Declaration for the Unit Under Test (UUT)
    15.  
    16.     COMPONENT test1
    17.     PORT(
    18.          clk : IN  std_logic;
    19.          input1 : IN  std_logic;
    20.          input2 : IN  std_logic;
    21.          output : OUT  std_logic
    22.         );
    23.     END COMPONENT;
    24.    
    25.  
    26.    --Inputs
    27.    signal clk : std_logic := '0';
    28.    signal input1 : std_logic := '0';
    29.    signal input2 : std_logic := '0';
    30.  
    31.      --Outputs
    32.    signal output : std_logic;
    33.  
    34.    -- Clock period definitions
    35.    constant clk_period : time := 1 ns;
    36.  
    37. BEGIN
    38.  
    39.     -- Instantiate the Unit Under Test (UUT)
    40.    uut: test1 PORT MAP (
    41.           clk => clk,
    42.           input1 => input1,
    43.           input2 => input2,
    44.           output => output
    45.         );
    46.  
    47.    -- Clock process definitions
    48.    clk_process :process
    49.    begin
    50.         clk <= '0';
    51.         wait for clk_period/2;
    52.         clk <= '1';
    53.         wait for clk_period/2;
    54.    end process;
    55.  
    56.  
    57.    -- Stimulus process
    58.    stim_proc: process
    59.    begin        
    60.       -- hold reset state for 100 ns.
    61.       wait for 10 ns;    
    62.         input1 <= '0';
    63.         input2 <= '0';
    64.        
    65.         wait for 20 ns;
    66.         input1 <= '0';
    67.         input2 <= '1';
    68.        
    69.         wait for 30 ns;
    70.         input1 <= '1';
    71.         input2 <= '0';
    72.        
    73.         wait for 40 ns;
    74.         input1 <= '1';
    75.         input2 <= '1';
    76.  
    77.    
    78.    end process;
    79.  
    80. END;
    81.  
    but after simulating the behavioural Model i am getting the value of
    clk = U
    input1 = U
    input2 = U
    output = U
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    I made a simple change to your clock and it works. However, as you have written the test bench, there is no end, so the simulation goes on forever.


    Code ( (Unknown Language)):
    1.  
    2.  LIBRARY ieee;
    3.  USE ieee.std_logic_1164.ALL;
    4.  
    5.  -- Uncomment the following library declaration if using
    6.  -- arithmetic functions with Signed or Unsigned values
    7.  --USE ieee.numeric_std.ALL;
    8.  
    9.  ENTITY test IS
    10.  END test;
    11.  
    12.  ARCHITECTURE behavior OF test IS
    13.  
    14.  -- Component Declaration for the Unit Under Test (UUT)
    15.  
    16.  COMPONENT test1
    17.  PORT(
    18.  clk : IN std_logic;
    19.  input1 : IN std_logic;
    20.  input2 : IN std_logic;
    21.  output : OUT std_logic
    22.  );
    23.  END COMPONENT;
    24.  
    25.  --Inputs
    26.  signal clk : std_logic := '0';
    27.  signal input1 : std_logic := '0';
    28.  signal input2 : std_logic := '0';
    29.  --Outputs
    30.  signal output : std_logic;
    31.  -- Clock period definitions
    32.  constant clk_period : time := 1 ns;
    33.  
    34.  BEGIN
    35.  
    36.  -- Instantiate the Unit Under Test (UUT)
    37.  uut: test1 PORT MAP (
    38.  clk => clk,
    39.  input1 => input1,
    40.  input2 => input2,
    41.  output => output
    42.  );
    43.  -- Clock process definitions
    44.  [B]clk <= NOT clk after 1ns;[/B]
    45.  -- Stimulus process
    46.  stim_proc: process
    47.  begin
    48.  -- hold reset state for 100 ns.
    49.  wait for 10 ns;
    50.  input1 <= '0';
    51.  input2 <= '0';
    52.  
    53.  wait for 20 ns;
    54.  input1 <= '0';
    55.  input2 <= '1';
    56.  
    57.  wait for 30 ns;
    58.  input1 <= '1';
    59.  input2 <= '0';
    60.  
    61.  wait for 40 ns;
    62.  input1 <= '1';
    63.  input2 <= '1';
    64.  
    65.  end process;
    66.  END;
    67.  
     
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