VHDL Error 10500 Problem

Discussion in 'Embedded Systems and Microcontrollers' started by audioschlumpf82, Apr 11, 2013.

  1. audioschlumpf82

    Thread Starter New Member

    Apr 11, 2013
    2
    0
    Hi

    i'm new in VHDL and i try to compile this Code. I don't understand the error. First i tried google but there was no success to my problem
    Can some one give me a hint? I'm using Quartus II.

    Code (Text):
    1.  
    2.  
    3. library ieee;
    4. use ieee.std_logic_1164.all;
    5. use ieee.numeric_std.all;
    6.  
    7.  
    8. entity LUTmuxMxN is
    9.  
    10.     generic(
    11.        
    12.         --Zaehlergrenzen
    13.         min             :        natural := 0;    
    14.         max            :        natural := 255    
    15.     );
    16.  
    17.     port(
    18.    
    19.         -- Systemclock => 2kHz
    20.         clk            :        in std_logic;
    21.        
    22.         --KEY[0] und KEY[1]
    23.         taste0        :        in std_logic;
    24.         taste1        :        in std_logic;
    25.        
    26.         --Helligkeitswert der ausgegeben wird
    27.         brightness    :        out integer range min to max                
    28.     );
    29. end entity;
    30.  
    31.  
    32. architecture verhalten of LUTmuxMxN is
    33.  
    34.     signal richtung : integer;    
    35.     signal reset_n, enable_heller, enable_dunkler : std_logic;
    36.    
    37.     begin
    38.    
    39.     -- Erkennen ob der LED heller oder dunkler
    40.     -- eingestellt werden soll
    41.    
    42.     poti_richtung:    process(taster0, taster1)
    43.    
    44.                     begin
    45.            
    46.                         --    Beide Taster gedrückt Reset
    47.                         if (rising_edge(taster0) and rising_edge(taster1)) then
    48.                             reset_n = '1';
    49.        
    50.                         --    Taster 0 (KEY[0]) gedrückt LED leuchtet heller
    51.                         else if rising_edge(taster0) then
    52.                             richtung <= 1;
    53.                             enable_heller <= '1';
    54.                            
    55.                         --    Taster 1 (KEY[1]) gedrückt LED leuchtet dunkler
    56.                         else if rising_edge(taster1) then
    57.                             richtung <= -1;
    58.                             enable_dunkler <= '1';
    59.                            
    60.                         --    zur Vermeidung von Latches, da der Process asynsron
    61.                         --    läuft
    62.                         else
    63.                             richtung <= 0;
    64.                             enable_heller <= '0';
    65.                             enable_dunkler <= '0';
    66.                         end if;
    67.                        
    68.                 end process;
    69.    
    70.     poti:        process(clk)
    71.  
    72.                     variable counter :    integer range min to max;
    73.    
    74.                         begin
    75.                        
    76.                             --syncroner Update mit Systemtakt
    77.                             if (rising_edge(clk)) then
    78.                            
    79.                                 if reset_n = '1' then
    80.                                     counter := 0;
    81.                                                            
    82.                                 -- heller
    83.                                 else if enable_heller = '1' then
    84.                                     counter := counter + richtung;
    85.                                
    86.                                 -- dunkler
    87.                                 else if enable_dunkler = '1' then
    88.                                     counter := counter + richtung;
    89.                                
    90.                                 end if;
    91.                                
    92.                             end if;
    93.                    
    94.                         brightness <= counter;
    95.                
    96.                 end process;
    97.                
    98. end verhalten;
    99.  
    100. [Error messages from Quartus II]
    101.  
    102. Info: *******************************************************************
    103. Info: Running Quartus II 32-bit Create Symbol File
    104.     Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
    105.     Info: Processing started: Thu Apr 11 16:15:35 2013
    106.     Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
    107.     Info: Processing started: Thu Apr 11 16:15:35 2013
    108. Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DeltaSigmaTop -c DeltaSigmaTop --generate_symbol=C:/Users/Workstation/Desktop/DSF/DeltaSigma/LUTmuxMxN.vhd
    109. Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(32) near text "signal";  expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement
    110. Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(33) near text "signal";  expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement
    111. Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(50) near text "=";  expecting "(", or "'", or "."
    112. Error: Quartus II 32-bit Create Symbol File was unsuccessful. 3 errors, 0 warnings
    113.     Error: Peak virtual memory: 332 megabytes
    114.     Error: Processing ended: Thu Apr 11 16:15:39 2013
    115.     Error: Elapsed time: 00:00:04
    116.     Error: Total CPU time (on all processors): 00:00:03
    117.     Error: Peak virtual memory: 332 megabytes
    118.     Error: Processing ended: Thu Apr 11 16:15:39 2013
    119.     Error: Elapsed time: 00:00:04
    120.     Error: Total CPU time (on all processors): 00:00:03
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    I don't see anything wrong, but I wonder of Quartus expects the module name after "end entity" I've always included the name, so I don't know if quartus will like what you've done or not.
     
  3. audioschlumpf82

    Thread Starter New Member

    Apr 11, 2013
    2
    0
    THX for your answser. Actually the error was in a second file. So i didn't read the error message very well :/.
     
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