I'm a VHDL newbie and am trying to make a fairly simple circuit consisting of several smaller components which I tie together in the main module. I'm going to make this a fairly generic question because I'm not so sure the details matter too much. If they do, I'll happily post what I can.

Basically I have a component with some output which ties directly into the entity's out ports along with some other components which I would like to receive feedback from that aforementioned component. Some of these signals I would also like to perform combination logic on before feeding the input back. What is the best way to do this? I get an error in ModelSim stating cannot read output. If I try to port map the component's outputs to multiple signal lines I also get an error. I can think of a work around, but I didn't know if there was a better solution. Thanks in advance.

EDIT:
So my workaround works, which was to just create a bunch more intermediate signal lines which I used in my combinational logic. I guess what I was wanting to know was if you could directly access an included entity's (a component's) output lines.

 

No, as a limitation to VHDL, you cannot read values from an output. You can, however read from an inout port, or a buffer (though support for a buffer signal is a little sketchy). The typical workaround, that you seem to have found, is to assign the output to an internal signal that is set and read at will.

Also, are you suggesting that you are connecting outputs together?

 

Thanks! That answers the question. Sometimes VHDL seems so intelligent in how it can turn some simple statements into a complex sequential circuit. Yet at other times it seems so primitive. Thanks for confirming though. For the record, I was not trying to tie multiple outputs together, as that would violate all that I know about digital design (save for with the help of a tristate buffer). I was just trying to send the output to multiple locations, one of which was to the final output of the circuit and the other which would reset a counter. Thanks again.

 

buffer is what you want.

 

buffer is what you want.

If you use the buffer type, be sure to set the compiler to use, as a minimum, the 2002 version of VHDL as buffers were not well supported before then. I know some compilers will default to the '93 version, meaning you'd need to change the version the compiler is compiling against.