Vhdl - combining components

Discussion in 'Programmer's Corner' started by Zinbielvhd, Jul 29, 2007.

  1. Zinbielvhd

    Thread Starter New Member

    Jul 29, 2007
    I'm trying to create a mips R2000-like architecture in behavioral vhdl.
    I've written the code for several parts (the ALU, the FSM, etc) but I am a bit confused how to make them work together.

    I understand I have to use structural vhdl in the highest level (say cpu.vhd) and I know how to embed a component into a bigger one but how can I assign the output of a single component to the input of another.

    For example I know how to assign the clock signal that exists in the highest level to whichever component needs it, but I don't know how to assign the Instruction Memory output (which obviously is not an input of the high level module) to the Instruction Register unit without the highest level module acting as a dispatcher (reading the IM output and then writing it to the IR).

    I hope I've clearly stated by problem/confusion.
    Any help is deeply appreciated.
  2. mrmeval

    Distinguished Member

    Jun 30, 2006
  3. Zinbielvhd

    Thread Starter New Member

    Jul 29, 2007
    Thank you mrmeval but I already found out what to do :)
    The highest level module has to read the outputs of lower level ones into signals and then pass them as input.
    There might not be a way to connect the modules directly but in the end it may even be the same thing when synthesizing the code.

    Thanks again for your interest :)
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    Use the port map on the component intantiation.