VHDL coding

Discussion in 'Embedded Systems and Microcontrollers' started by haran, May 6, 2008.

  1. haran

    Thread Starter Active Member

    Apr 6, 2008
    42
    0
    i need to find out how to make a down counter using vhdl coding. There is one input and the output will be to a seven segment display using a maxplus+ device and i can only use either when statement or bit assignment. any tips or any websites providing tutorial for this kind of stuf.When the switch is pressed the program will start to count down from 9 till 0 and thats it
     
  2. ametso

    Member

    Apr 30, 2008
    13
    0
    I had a few moment a free time and I wrote a very simple vhdl code about the down counting as an examble (see attachment). It's fully functional - exept I made some syntax error into the code (bad bad me). Exploring those errors you will learn something about vhdl.

    Note! even that the code is functional you have to be care of about bouncing of the input signal, how to generate count clock, etc.
    So - remember that this code is only an examble about VHDL coding.

    By the way - change the .txt file extension to the .vhd
     
  3. haran

    Thread Starter Active Member

    Apr 6, 2008
    42
    0
    thanks for your coding...i just finished my version of the counter. its a bit tricky i used a 4 bit synchronous binary counter to generate binary code from 0 till 15 then i built a block diagram to take the output from the binary counter and invert it using when statement and then putting the output to a bcd to seven segment decoder. it works actually i have added the file with this u can check it out if u want.;). open the trial.gdf its the main file. please give me ur feedback about it..tanks..
     
  4. ametso

    Member

    Apr 30, 2008
    13
    0
    I have few comment.

    First of all. I don't have a MaxPlus software and I'm not sure does the Quartus translated your "trial" project correct... And actually there is not much code for commenting :0)

    But any way. The row 38 in counter.vhd

    37: if clear = '1' then
    38: Pre_Q <= Pre_Q - Pre_Q;
    39: elsif (clock='1' and clock'event) then

    is too complex. You can use word "others" to set each of bit to one state (0 or 1). Like..

    37: if clear = '1' then
    38: Pre_Q <= (others=>'0')
    39: elsif (clock='1' and clock'event) then

    And your counter not stop untill the button is released (might be this phenomena is included in your specs)

    Finally - in professional manner - try to avoid a graphical presentation of your design. I mean those block designing. Because if you use graphs then your design is marriaged to one specific tool and manufacturer. Only allowed block diagram is the top level of the design... Okay this is my opinion but it base to real life.
     
  5. Reshma

    Active Member

    Mar 11, 2007
    54
    0
    You can also try an up-down counter, by making use of a control bit viz ud (up/down):
    Code ( (Unknown Language)):
    1. if(clock'event and clock = '1') then
    2.   if (ud = '1') then
    3.    Pre_Q <= Pre_Q + 1;
    4.     elsif(ud = '0') then
    5.    Pre_Q <= Pre_Q - 1;
    6.   end if;
    7. end if;
    8.  
     
  6. ametso

    Member

    Apr 30, 2008
    13
    0
    And If you like be more effisient about writing a code then you can reduse Resmas code litle bit...

    Because there is only two posibities to update Pre_Q (debending a value of ud) in Reshmas code the "elsif" if can be changed to "else". So the Resmas code can be re write to form:

    Code ( (Unknown Language)):
    1. if(clock'event and clock = '1') then
    2.   if (ud = '1') then
    3.     Pre_Q <= Pre_Q + 1;
    4.   else
    5.     Pre_Q <= Pre_Q - 1;
    6.   end if;
    7. end if;
    8.  
    And this point one trick can be used in VHDL. The "else" state can be writen always before "if" sentence. As like a "default assigment". So the code can be redused more.

    Code ( (Unknown Language)):
    1. if(clock'event and clock = '1') then
    2.   Pre_Q <= Pre_Q - 1; -- this is default counting direction
    3.   if (ud = '1') then
    4.     Pre_Q <= Pre_Q + 1;
    5.   end if;
    6. end if;
    7.  
    Okay... this is only a coding habit what I use likely. Because it tells what hapen in normally and after that is writen all conditions what can change the default assigment.
     
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