VHDL coding error!

Discussion in 'Homework Help' started by lemoneyes, Jun 19, 2009.

  1. lemoneyes

    Thread Starter New Member

    Apr 20, 2009
    6
    0
    hello dudes
    i have an error,, underlined sentence above this source
    error message is "HAlF_PERIOD is not agree with its usage for BOOLEAN TYPE
    while i can see this message, i can't fix it,,

    my tool is quatus ll 9.0





    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    ENTITY tb_dice IS
    END tb_dice;
    ARCHITECTURE behavior OF tb_dice IS
    COMPONENT dice_game_core
    PORT(
    clk : IN std_logic;
    rst : IN std_logic;
    roll : IN std_logic;
    win : OUT std_logic;
    lose : OUT std_logic;
    dice0 : OUT std_logic_vector(2 downto 0);
    dice1 : OUT std_logic_vector(2 downto 0);
    pointR : out std_logic_vector(3 downto 0)
    );
    END COMPONENT;
    SIGNAL clk : std_logic;
    SIGNAL rst : std_logic;
    SIGNAL roll : std_logic;
    SIGNAL win : std_logic;
    SIGNAL lose : std_logic;
    SIGNAL dice0 : std_logic_vector(2 downto 0);
    SIGNAL dice1 : std_logic_vector(2 downto 0);
    signal pointR : std_logic_vector(3 downto 0);

    constant HALF_PERIOD : time := 10 ns;
    constant PERIOD : time := 20 ns;
    BEGIN
    uut: dice_game_core PORT MAP(
    clk => clk,
    rst => rst,
    roll => roll,
    win => win,
    lose => lose,
    dice0 => dice0,
    dice1 => dice1, pointR=>pointR
    );
    clkgen: process
    begin
    clk <= '0'; wait for HALF_PERIOD ;
    clk <= '1'; wait for HALF_PERIOD ;
    end process ;
    stim: process
    begin
    rst <= '1'; -- reset
    roll <= '0'; -- disable
    wait for PERIOD *2;
    rst <= '0'; -- release reset (start run)
    wait for PERIOD ;
    roll <= '1'; -- enable roll dice
    wait for 5 * PERIOD ;
    roll <= '0'; -- disable & sum = 7 => win
    wait for 2* PERIOD;
    rst <= '1';
    wait for PERIOD;
    rst <= '0';
    roll <= '1';
    wait for 3 * PERIOD;
    roll <= '0'; -- disable rolling & sum = 5 => lose
    wait for 2 * PERIOD;
    rst <= '1';
    wait for PERIOD;
    rst <= '0';
    roll <= '1';
    wait for 11 * PERIOD; -- sum = 8
    roll <= '0'; -- disable;
    wait for 3 * PERIOD; -- 1 * PERIOD
    roll <= '1'; -- enable rolling
    wait for 6 * PERIOD;
    roll <= '0'; -- sum = 8 ==> save
    wait for PERIOD ;
    roll <= '1';
    wait for 4 * PERIOD;
    roll <= '0'; -- sum = 8 --> win
    wait for 2* PERIOD;
    rst <= '1';
    wait for PERIOD;
    roll <= '1'; rst <= '0';
    wait for 4 * PERIOD ;
    roll <= '0'; -- sum = 6 => save;
    wait for PERIOD;
    roll <= '1';
    wait for PERIOD ;
    roll <= '0'; -- sum = 7 => lose
    wait for 2 * PERIOD;
    rst <= '1';
    wait for PERIOD;
    rst <= '0';
    roll <= '1';
    wait for 6 *PERIOD;
    roll <= '0';
    wait for 2*PERIOD;
    roll <= '1';
    wait for 5* PERIOD;
    roll <= '0';
    wait;
    end process;
    END behavior;
     
    Last edited: Jun 19, 2009
  2. scythe

    Active Member

    Mar 23, 2009
    49
    5
    One thing you may have forgotten is that a process statement is viewed as one indivisible statement, that is, all the sequential statements in a process are executed at the end of the entire process. In this case, it is my guess that you are always declaring the clock as 1, since the process will only execute this statement, as it is the last assignment to "clk".

    I don't have much experience with "wait for" statements... I have heard however that "wait for" statements are generally not synthesizable in a design. So if your problems are with synthesis, try to substitute the "wait for" statements with something else.

    Aside from that, I'm not sure what it would be. My coding style is different.

    BTW, did you choose your name "lemoneyes" from a cartoon?
     
  3. StayatHomeElectronics

    Well-Known Member

    Sep 25, 2008
    864
    40
    Are you trying to compile for simulation (ModelSim) or synthesize for putting on the Altera device?

    If for simulation, verify that the simulator has implemented wait...for statements and not just wait...until statements which asks for a boolean.

    If you are trying to synthesis to download to the chip, the Altera part has no way of knowing what 20 ns is. You need to provide some clock to the device. It can not synthesize its own given to input.
     
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