VHDL asynchronous clear

Discussion in 'Programmer's Corner' started by gammaman, Mar 29, 2009.

  1. gammaman

    Thread Starter Member

    Feb 14, 2009
    29
    0
    How would I modify the following code so that clear is asynchronous?

    Code ( (Unknown Language)):
    1.  
    2. Library ieee;
    3. Use ieee.std_logic_1164.all;
    4. Use ieee.std_logic_arith.all;
    5. Use ieee.std_logic_unsigned.all;
    6.  
    7. Untity Four_Bit_Register is
    8.     Port (
    9.         Clear        : in  std_logic;
    10.         Inc           : in  std_logic; -- x
    11.             Clock       : in  std_logic;
    12.     Cnt_in        : in std_logic_vector(3 downto 0);      
    13.             Cnt_out    : out std_logic_vector(3 downto 0);
    14.     Load            : in std_logic);    
    15. End Four_Bit_Register;
    16.  
    17. Architecture Four_Bit_Register_Arch of Four_Bit_Register is
    18.  
    19. Signal Cnt    : std_logic_vector (3 downto 0);    
    20.  
    21. Begin
    22.  Cnt_out <= Cnt;
    23.  
    24.   Count : Process( Clear, Inc, Clock, Load)
    25.  
    26. Begin
    27.    
    28.     if clock'event and Clock = '1' then
    29.    
    30.     if Clear = '1' then
    31.              Cnt    <= "0000";
    32. elsif Load = '1' then
    33.         Cnt <= Cnt_in;
    34. elsif Inc = '1' then
    35.               Cnt    <= Cnt + "0001";
    36.          else
    37.              Cnt    <= Cnt;
    38.             End if;    
    39. End if;
    40. End process;
    41.  
    42. end Four_Bit_Register_Arch;
    Would I just change Cnt<="0000";
    To Cnt<="1111";
     
  2. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Take the clear function out of the process branch or put it before the clock .
     
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