VHDL and VGA/XSGA Output

Discussion in 'Embedded Systems and Microcontrollers' started by colourblind82, Dec 7, 2006.

  1. colourblind82

    Thread Starter New Member

    Dec 7, 2006
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    Hi all,

    I'm new here... i would like to ask if anyone knows how to use the XSGA Output of Xilinx Virtex II Pro. I've connected it to a monitor and tried some codes to test it but it's not working. I need to use it using VHDL codes. Please help...

    Cheers~~~
     
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
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    Are you referring to XSGA output from XUP board?
     
  3. colourblind82

    Thread Starter New Member

    Dec 7, 2006
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    Yes. It's the XSGA output from XUP. I saw that there is a reference design from Xilinx website but it's not in VHDL.
     
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
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    Download the XUP manual from either Xilinx or Digilent site. It has the connection and signal diagram of the FPA -> DAC signals. You can get the DAC datasheet and VGA timing and then derived the necessary timing and signals to create the VGA signals.

    There are Verilog examples available, again either from Xilinx or Digilent sites.
     
  5. colourblind82

    Thread Starter New Member

    Dec 7, 2006
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    I saw some verilog examples but I am not good in verilog. Just started to learn VHDL.

    I found these codes from the web. But it doesnt work on my board. Please help...

    -- VHDL Architecture ece412_lib.mp3_1.untitled
    --
    -- Created:
    -- by ? Seunghoon Kim - skim41.stdt (eesn39.ews.uiuc.edu)
    -- at - 12:31:12 03/18/05
    --
    -- using Mentor Graphics HDL Designer(TM) 2004.1 (Build 41)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;
    USE ieee.std_logic_arith.all;
    USE ieee.std_logic_unsigned.all;
    ENTITY mp3_1 IS
    PORT(
    CLK_100MHZ : IN std_logic;
    CLK_32MHZ : IN std_logic;
    PB_DOWN : IN std_logic;
    PB_ENTER : IN std_logic;
    PB_LEFT : IN std_logic;
    PB_RIGHT : IN std_logic;
    PB_UP : IN std_logic;
    XUP_DIP_SW : IN std_logic_vector (3 DOWNTO 0);
    VGA_COMP_SYNCH : OUT std_logic;
    VGA_HSYNCH : OUT std_logic;
    VGA_OUT_BLANK_Z : OUT std_logic;
    VGA_OUT_BLUE : OUT std_logic_vector (7 DOWNTO 0);
    VGA_OUT_GREEN : OUT std_logic_vector (7 DOWNTO 0);
    VGA_OUT_PIXEL_CLOCK : OUT std_logic;
    VGA_OUT_RED : OUT std_logic_vector (7 DOWNTO 0);
    VGA_VSYNCH : OUT std_logic;
    XUP_LED : OUT std_logic_vector (3 DOWNTO 0);
    CLK_25OUT : out std_logic; --
    CLK_25FLAG : out std_logic --
    );
    -- Declarations
    END ENTITY mp3_1 ;
    --
    ARCHITECTURE untitled OF mp3_1 IS
    signal rowcount : integer range 0 to 1023;
    signal columncount : integer range 0 to 1023;
    signal CLK_25MHZ : std_logic;
    signal cnt2clk : std_logic_vector(2 downto 0) := "000";
    signal gradient : std_logic_vector(9 downto 0);
    BEGIN
    VGA_COMP_SYNCH <= '1';

    clk_convert : process (CLK_100MHZ)
    begin

    if (CLK_100MHZ = '1' and CLK_100MHZ'Event) then
    cnt2Clk <= cnt2Clk + 1;
    end if;
    end process;

    CLK_25MHZ <= cnt2Clk(1);
    CLK_25OUT <= clk_25MHZ; --
    VGA_OUT_PIXEL_CLOCK <= cnt2clk(1);
    count : process (CLK_25MHZ)
    begin

    if (CLK_25MHZ = '1' and CLK_25MHZ'EVENT) then
    columncount <= columncount + 1;
    end if;
    if (columncount > 800) then
    columncount <= 1;
    rowcount <= rowcount + 1;
    end if;
    if (rowcount >= 520) then
    rowcount <= 1;
    end if;
    end process;

    syncout : process (clk_25MHZ)
    begin

    if (CLK_25MHZ = '1' and CLK_25MHZ'EVENT) then
    if (rowcount = 494) then -- Vsynch timing --if (rowcount >= 489 and rowcount < 491) then -- Vsynch timing --if (rowcount = 494) then -- Vsynch timing
    VGA_VSYNCH <= '0';
    else
    VGA_VSYNCH <= '1';
    end if;
    if (columncount >= 660 and columncount < 756) then -- Hsynch timing --if (columncount >= 656 and columncount < 752) then -- Hsynch timing --if (columncount >= 660 and columncount < 756) then -- Hsynch timing
    VGA_HSYNCH <= '0';
    else
    VGA_HSYNCH <= '1';
    end if;
    if (rowcount > 480 or columncount > 640) then -- blank
    VGA_OUT_BLANK_Z <= '0';
    else
    VGA_OUT_BLANK_Z <= '1';
    end if;
    end if;
    end process;

    display : process
    begin

    wait until (CLK_25MHZ = '1' and CLK_25MHZ'EVENT);
    if (rowcount >= 60 and rowcount < 320) then -- color code
    if (columncount >= 576) then
    VGA_OUT_RED <= X"00";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"00";
    elsif (columncount >= 480) then
    VGA_OUT_RED <= X"00";
    VGA_OUT_BLUE <= X"FF";
    VGA_OUT_GREEN <= X"FF";
    elsif (columncount >= 320) then
    VGA_OUT_RED <= X"FF";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"00";
    elsif (columncount >= 160) then
    VGA_OUT_RED <= X"FF";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"FF";
    elsif (columncount >= 64) then
    VGA_OUT_RED <= X"FF";
    VGA_OUT_BLUE <= X"FF";
    VGA_OUT_GREEN <= X"00";
    else
    VGA_OUT_RED <= X"00";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"00";
    end if;
    elsif (rowcount >= 320 and rowcount < 420) then
    if (columncount >= 64 and columncount < 576) then
    gradient <= CONV_STD_LOGIC_VECTOR(columncount - 64, 10); -- gradient calculation
    VGA_OUT_RED <= gradient(8 downto 1);
    VGA_OUT_BLUE <= gradient(8 downto 1);
    VGA_OUT_GREEN <= gradient(8 downto 1);
    else
    VGA_OUT_RED <= X"00";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"00";
    end if;
    else
    VGA_OUT_RED <= X"00";
    VGA_OUT_BLUE <= X"00";
    VGA_OUT_GREEN <= X"00";
    end if;
    end process;
    END ARCHITECTURE untitled;
     
  6. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
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    Well... it doesn't work is not exactly a helpful description of what's actually happening.

    What I am suggesting is to look on how to implement the function, either from the Verilog examples or from the XUP manual. It might take some time, but that is the best way to go forward.

    There are only several things that you need to implement to get a rudimentary VGA display. First is to check that you are sending the correct signals to the VGA system. For example the blanking signal, horizontal and vertical synch signals and then the RGB signal. Make sure your pin assignments are correct and also the frequencies of the signals follow the VGA timing.

    I have no idea whether that code above will work or not, a lot depend on your configurations as well as the code itself. Synthesising the code successfully doesn't guarantee it'd work if the systems are not exactly the same.
     
  7. colourblind82

    Thread Starter New Member

    Dec 7, 2006
    6
    0
    I've finally got the VGA output linked up... Thanks for all your help... =)
     
  8. ganesh_421

    New Member

    Mar 13, 2008
    2
    0


    friend please help me. i'm also facing the same problem,can u give me the idea about the VHDL code for VGA interface please. waiting for u r reply friend.
     
  9. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    I'm doubtful of a reply, it was from a long time ago :(

    Steve
     
  10. ganesh_421

    New Member

    Mar 13, 2008
    2
    0
    no sir,
    i'm facing problem while interfacing VGA port in XUP, can i've any support in VHDL please.
     
  11. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
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