VHDL adding two registers

Discussion in 'Programmer's Corner' started by gammaman, Apr 3, 2009.

  1. gammaman

    Thread Starter Member

    Feb 14, 2009
    29
    0
    How would I add to registers together so that A=A+B.

    This is what I have so far.

    Code ( (Unknown Language)):
    1.  
    2. Library ieee;
    3. Use ieee.std_logic_1164.all;
    4. Use ieee.std_logic_arith.all;
    5. Use ieee.std_logic_unsigned.all;
    6.  
    7. Entity  Four_Bit_Register is
    8.     Port (
    9.         Clear        : in  std_logic;
    10.         Inc           : in  std_logic; -- x
    11.         Clock       : in  std_logic;
    12.         Cnt_in        : in std_logic_vector(3 downto 0);      
    13.         Cnt_out        : out std_logic_vector(3 downto 0);
    14.         Load        : in std_logic);    
    15. End Four_Bit_Register;
    16.  
    17.  
    18.  
    19.  
    20. Architecture Four_Bit_Register_Arch of Four_Bit_Register is
    21.  
    22. Signal Cnt,A,B : std_logic_vector (3 downto 0);    
    23.  
    24. Begin
    25.  Cnt_out <= Cnt;
    26.  
    27.   Count : Process( Clear, Inc, Clock, Load)
    28.  
    29. Begin
    30.    
    31.     if clock'event and Clock = '1' then
    32.        A<=A+B;
    33.     if Clear = '1' then
    34.              Cnt    <= "0000";
    35.     elsif Load = '1' then
    36.         Cnt <= Cnt_in;
    37.     elsif Inc= '1' then
    38.               Cnt    <= Cnt + "0001";
    39.          else
    40.              Cnt    <= Cnt;
    41.             End if;    
    42. End if;
    43. End process;
    44.  
    45. end Four_Bit_Register_Arch;
    46.  
     
  2. DualCortex

    New Member

    Apr 3, 2009
    2
    0
    A <= std_logic_vector(signed(A) + signed(B));

    The compiler will synthesize an adder accordingly.
     
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