very basic VHDL code that is driving me crazy: two AND gates with a NOT gate

Discussion in 'Programmer's Corner' started by dig1, Mar 26, 2009.

  1. dig1

    Thread Starter Member

    Jul 31, 2008
    18
    0
    Hi folks. the circuit below on the picture is what i wanted to implement. I have several issues.

    ok, AN1 and BN1 i wanted to set them as internal signals.
    Cout is supposed to be an out.

    the AND1 module is supposed to be a module that could be [​IMG]instantiated to to describe AND3. In all honesty, i wrote the code not understanding fully the signal relationship. it compiles fine and would run fine if i could figure out SONATA to actually display the correct waveform. right now sonata is not showing anything. By the way, the ENTITIES AND1 and NOT1 are saved as files each to be compiled together later.
    [​IMG]
    AND1.VHDL

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity and1 is
    port (
    a: in std_logic;
    b: in std_logic;
    cout: out std_logic
    );
    end and1;

    architecture rtl of and1 is
    begin
    cout <= (a and b) ;
    end rtl;

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity not1 is
    port (
    b: in std_logic;
    bnot: out std_logic
    );
    end not1;

    architecture rtl of not1 is
    begin
    bnot <= not b ;
    end rtl;

    AND3.VHDL

    architecture and3 of and1 is
    signal an1, bn1: std_logic;
    component not1 port
    ( b: in std_logic;
    bnot: out std_logic);
    end component;
    component and1 port
    (a,b: in std_logic;
    cout: out std_logic);
    end component;

    begin
    U1: not1 port map (b, bn1);
    U2: and1 port map (a,b,an1);
    U3: and1 port map (an1,bn1,cout);
    end and3;

    Currently, everything is compiling fine. i don't know what's wrong with Sonata but the signals are not showing up in the simulation (as waveforms; i have the free version) but if it's compiling fine i am not worried much. but i am still bothered by a lot of things that are not clear to me:

    a) i am not understanding the component declarations. what's the purpose? those in and out signals, for the NOT1 and AND1, why do they need to be there? can't they be changed to some other variables

    b) am i correct in stating that i don't need to declare an entity in AND3 because the structure has been declared because AND3 and AND1 are the same gates and no need to describe the structure thus but WOULD HAVE TO INSTANTIATE the gate by doing AND3?

    c) in the entity descriptions,(AND1.VHDL & NOT1.VHDL) if the Output of the gates DOES NOT END UP BEING AN INTERNAL SIGNAL would that mean that i have to carry that also in the architecture file's declration?

    d) is what i wrote correct?

    i am not new to programming but hell, this really blows. i don't even know what the hell people were thinking when they were coming up with this. Verilog is i think from what i have seen simpler, but the lady doesn't know it so we are stuck learning this. Any help would be appreciated.

    BIG QUESTION I have is (which i am not able to find an answer easily from Andersen's book or another book i found online) is, when i am declaring entities or structures that are to be instantiated later, what is the relationship between the variables there, and the variables to be used in the component declaration and Architecture declaration?
    is component like a parts list?
    NB: i know for a fact this could be written simpler but i really needed to understand this to write a code for a project

    sorry this is long....
     
  2. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    You chose a rather odd combinations of gates to experiment with.

    If "a" is a logic low, "cout" will be low.

    If "a" is a logic high, then things get a bit iffy.
    In an ideal circuit, with zero rise/fall times and zero propagation delays, toggling "b" high or low will still result in "cout" being low; you'll never see anything but a low level cout.

    "Propagation delay" is the amount of time it takes for a change on the input to appear on the output of a device; usually given on the order of nanoseconds.

    If the propagation delays through the AND gates is different than through the inverter, you may see a brief positive pulse at cout, equal to the difference of the propagation delay. If the pulse occurs when "b" transitions from low to high, the AND gate has the shorter propagation delay; if the pulse occurs when "b" transitions from high to low, the inverter has the shorter propagation delay.

    Slow rise/fall times can cause odd things to occur if the logic device does not have Schmitt trigger inputs. The longer an input voltage stays at an "indeterminite" level, the more opportunity there is for faulty output.

    I'm not familiar with the software package you're using; just pointing out that the logic you're attempting to implement may evalute to a logic low output no matter what combinations you give it, even though "real world" components and signals may give you a very different output.
     
  3. dig1

    Thread Starter Member

    Jul 31, 2008
    18
    0
    thanks very much for the reply... you are right but the issue that i am having is not concerned with per se the actual circuitry but the VHDL code... i actually wrote the following test bench code to test the first AND gate and that shoulld have gotten me High on COUT_i When A & B is High but i am not getting a result

    AND_tb.VHDL

    entity and_tb is
    end and_tb;

    architecture behavioral of and_tb is


    component and1 is
    port (
    a: in std_logic;
    b: in std_logic;
    cout: out std_logic
    );
    end component;

    signal a_i, b_i: std_logic;
    signal cout_i: std_logic;

    -- This connects the signals to the inputs of the 4-bit adder
    begin

    U1: and1
    port map(a_i, b_i, cout_i);


    a_i <= '1' after 10 ns, '1' after 40 ns, '0' after 55 ns, '1' after 65 ns;
    b_i <= '1' after 10 ns, '0' after 45 ns, '1'after 55 ns, '1' after 65 ns;

    end behavioral;






    is my test bench code correct?
     
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