verilog, verilogger, file with 'v' extension

Discussion in 'General Electronics Chat' started by PG1995, Oct 3, 2011.

  1. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Hi :)

    Yesterday, I borrowed a book from someone and the book had a companion CD. Out of curiosity, I checked out the CD's contents and also read the introduction pages of the book. The book said the CD contained Verilog HDL files for some of the examples in the book with the software Verilogger Pro, Waveform Viewer, etc.

    The files had 'v' extension which I wasn't able to open even after installing the Verilogger Pro. But I was successful in opening the file with the Notepad. The code below had the contents of one of the files.

    After little searching on the net I came to know that Verilog is hardware description language (HDL) and Verilogger Pro is a simulator. Does it mean that if a write a certain code then the simulator can tell me how that code will be implemented like which component you will need etc.? Is HDL primarily used for digital logic?

    How do I open that 'v' extension file?

    Please help me with the queries above. Thank you very much.

    Regards
    PG
     
  2. jwilk13

    Member

    Jun 15, 2011
    228
    12
    The one time I've seen Verilog HDL used was with an Altera FPGA, using the software Quartus II. I've never used or heard of Verilogger Pro, so I can't speak to that. Try Googling it and see what you come up with.
     
  3. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    There are two types of software concerning HDL: compilers and simulators.

    Compilers will construct a circuit based on your description. Usually they can be quite imaginative, if the description is abstract.

    Simulators will provide you the output of your circuit given an input, without worrying about the circuit's contents and their presentation.

    Some suites combine them both.

    HDL is mainly used for the design of VLSI systems, were modular development and pre-production testing is a must.
     
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  4. jwilk13

    Member

    Jun 15, 2011
    228
    12
    Also of note, you can download Quartus II here along with Altera's own Verilog HDL simulator software, ModelSim. The starter edition is free with no license required.
     
  5. rtay

    New Member

    Jul 27, 2011
    10
    2
    Hi,

    Like it was already described, verilog is a language that allows you to describe how you would like your hardware to behave. For example, you might specify the number of inputs to your hardware, the digital operation you would like to perform on the two inputs and produce an output out of the operation. In that manner, you can build multiple 'modules' that use digital logic. You put that in a .v file. The compiler looks at your descriptions in your .v and produces the digital devices that will carry out the operation you specified.

    The simulator allows you to see if the compiler has translated your description properly. So for example using modelsim, you can write another .v test file that describes the values of your inputs at certain times. The simulator takes your test file that contains descriptions of your inputs and applies them to your compiled original .v file and shows you the output you should expect out of your modules and hardware.

    Another tool in the hardware language is synthesizer. This performs the physical planning and implementation of your modules on your final hardware. Given a certain hardware that the synthesizer recognizes, it will allocate your .v code to what is physically available on the hardware. Finally once you are satisfied with the results of your simulator, you download your hardware description to your actual hardware using a programmer.
     
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  6. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Thank you, everyone, for the replies.

    I have MultiSim and Circuit Wizard programs. They both let you use gates in electric circuits. But I don't think they do what I describe below. Do they?

    I want a program in which I can drag-and-drop the gates etc. and then simply describe the inputs to see what the output should be.

    For example, suppose I have created the following circuit after dragging-and-dropping the NAND gates, then I state what the inputs would be to A, B, and C, and then the program tells me the output at Q.

    [​IMG]
     
  7. rtay

    New Member

    Jul 27, 2011
    10
    2
    Hi PG1995,

    I haven't used MultiSim and Circuit Wizard but here is how I think you can use verilog and programs associated with it to do what you described. Altera's Quartus, in addition to doing the verilog stuff, also allows you to draw block diagrams with the pick and drop method. You don't have to use verilog for this. You then compile your block diagram and tell the compiler that you will be using ModelSim to simulate it. So it compiles it and produces a corresponding VHDL/Verilog file from your block diagram that you can use in Modelsim. Now here is where I think you may need a description language. You write a test bench with a description of your inputs and timing conditions and compile that with your verilog file that was produced by the compiler from the block diagram. You then simulate your module and see the outputs in waveform.

    If there is a method of simulating your block diagram without using a text based test bench, I'm not familiar without it and I hope somebody else chimes in about it. Quartus used to let you simulate your modules directly without writing a test bench (the design is loaded with a list of inputs/outputs and other variables after compiling and inputs can be changed by right-clicking and assigning values to them). I don't know what happened to that. Maybe it is still out there somewhere in some program. Anyway, see the attached pictures for an illustration of this post.
    And here is a tutorial about it:
    http://edg.uchicago.edu/software/altera/quartus_tutorial/
     
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  8. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Thank you very much, rtay.

    I have been told that I can also do what I want to in Multisim or Circuit Wizard. I appreciate your help.

    My best wishes
    PG
     
  9. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Hi, again, :)

    If we have a mathematical function, say f(x) = y = 2x + x^2, we can graph it with a graphing calculator or with some math program. I'm going to learn some topics which involve Boolean functions and logic gates where gates are represented in terms of Boolean functions. For example, the given Boolean expression AB + A(B+C) + B(B+C) can be implemented using logic gates. Is there some software which I can use to do these things? I can't learn Verilog for this in such short time. In other words, is there some software which I can use to play around with Boolean algebra and logic gates? Thanks for your help and time.

    Regards
    PG
     
  10. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    Google Boole-Deusto. It's an experimental program that has all of the functions you need to create Boolean expressions plus an elementary circuit wizard.
     
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  11. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Hi

    There is something really wrong with the code of 4-bit four-to-one mux below. I have checked the code of 4-bit two-to-one mux separately and it works okay. It means that the error lies somewhere in the code for four-to-mux. You can see here that output Y3 is "1" when it should be "F", and it's "0" when it should be "A" and so on. Please help me with it. Thanks.

    Code ( (Unknown Language)):
    1.  
    2. //4-bit 2x1 Mux
    3.  
    4. module two_to_1_mux(Y,A,B,Sel,En);
    5.  
    6. input [3:0]A;
    7. input [3:0]B;
    8. input Sel,En;
    9. output [3:0]Y;
    10. reg [3:0]Y;
    11.  
    12. always @(En or Sel or A or B)
    13.   if(En==1)begin
    14.   if (Sel==0)
    15.   Y <= A;
    16.   else
    17.   Y <= B;
    18.   end
    19. endmodule
    20.  

    Code ( (Unknown Language)):
    1.  
    2. //4-bit 4 to 1 mux using 2 to 1 muxs
    3. //we will use the code for 2-to-1 mux given above for instantiation
    4.  
    5. module four_to_one(Y3,A,B,C,D,Sel,En);
    6.  
    7. input [3:0]A;
    8. input [3:0]B;
    9. input [3:0]C;
    10. input [3:0]D;
    11. input [1:0]Sel;
    12. input En;
    13. output [3:0]Y3;
    14.  
    15. two_to_1_mux mux1(Y1,A,B,Sel[0],En);
    16. two_to_1_mux mux2(Y2,C,D,Sel[0],En);
    17. two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);
    18. endmodule
    19.  
    20. //stimulus
    21.  
    22. module testbench;
    23.   reg [3:0]A;
    24.   reg [3:0]B;
    25.   reg [3:0]C;
    26.   reg [3:0]D;
    27.   reg [1:0]Sel;
    28.   reg En;
    29.   wire [3:0]Y3;
    30.  
    31.   four_to_one fourMux(Y3,A,B,C,D,Sel,En);
    32.  
    33.   initial
    34.   begin
    35.   A<=4'b1111;
    36.   B<=4'b1010;
    37.   C<=4'b1100;
    38.   D<=4'b0011;
    39.   En<=1;
    40.  
    41.   Sel=00;
    42.   #20 Sel=01;
    43.   #20 Sel=10;
    44.   #20 Sel=11;
    45.   #20 $finish;
    46.   end
    47. endmodule
    48.  
    Useful links:
    http://wiresharklabs.wordpress.com/2013/03/27/chapter-5-combinational-logic/

    Regards
    PG
     
    Last edited: Apr 16, 2014
  12. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    You have no declarations for Y1 and Y2. The simulator doesn't know what these are supposd to be.
     
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  13. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Thank you.

    I tried to mend the code but it's still not working. Could you please help me with it? Thanks.

    Errors:
    [​IMG]

    Code ( (Unknown Language)):
    1.  
    2. module four_to_one(Y3,A,B,C,D,Sel,En);
    3.  
    4. input [3:0]A;
    5. input [3:0]B;
    6. input [3:0]C;
    7. input [3:0]D;
    8.  
    9. input [1:0]Sel;
    10.  
    11. input En;
    12.  
    13. output [3:0]Y3;
    14.  
    15. output [3:0]Y1;  //addition
    16. output [3:0]Y2;  //addition
    17.  
    18.  
    19.  
    20. two_to_1_mux mux1(Y1,A,B,Sel[0],En);
    21.  
    22. two_to_1_mux mux2(Y2,C,D,Sel[0],En);
    23.  
    24. two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);
    25.  
    26. endmodule
    27.  
    28.  
    29. //stimulus
    30.  
    31. module testbench;
    32.  
    33.   reg [3:0]A;
    34.   reg [3:0]B;
    35.   reg [3:0]C;
    36.   reg [3:0]D;
    37.   reg [1:0]Sel;
    38.   reg En;
    39.   wire [3:0]Y3;
    40.  
    41.   wire [3:0]Y2;  //addition
    42.   wire [3:0]Y1;  //addition
    43.  
    44.  
    45.     four_to_one fourMux(Y3,A,B,C,D,Sel,En);
    46.         initial
    47.             begin
    48.                 A<=4'b1111;
    49.                 B<=4'b1010;
    50.                 C<=4'b1100;
    51.                 D<=4'b0011;
    52.                 En<=1;
    53.  
    54.                     Sel=00;
    55.                 #20 Sel=01;
    56.                 #20 Sel=10;
    57.                 #20 Sel=11;
    58.                 #20 $finish;
    59.             end
    60.  
    61. endmodule
    62.  
    63.  
     
  14. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Y1 & Y2 aren't port signals. Declare them as reg.

    Gotta run, I'll check back later today.
     
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  15. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    It's still not working! I declared them as registers. Please help me when you get time. Thanks.

    Errors:
    [​IMG]


    Code ( (Unknown Language)):
    1.  
    2. module four_to_one(Y3,A,B,C,D,Sel,En);
    3.  
    4. input [3:0]A;
    5. input [3:0]B;
    6. input [3:0]C;
    7. input [3:0]D;
    8.  
    9. input [1:0]Sel;
    10.  
    11. input En;
    12.  
    13. output [3:0]Y3;
    14.  
    15. reg [3:0]Y1;  //addition,
    16. reg [3:0]Y2;  //addition,
    17.  
    18.  
    19.  
    20. [COLOR="RoyalBlue"]two_to_1_mux mux1(Y1,A,B,Sel[0],En); // line 21
    21.  
    22. two_to_1_mux mux2(Y2,C,D,Sel[0],En); //line 23[/COLOR]
    23.  
    24. two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);
    25.  
    26. endmodule
    27.  
    28.  
    29. //stimulus
    30.  
    31. module testbench;
    32.  
    33.   reg [3:0]A;
    34.   reg [3:0]B;
    35.   reg [3:0]C;
    36.   reg [3:0]D;
    37.   reg [1:0]Sel;
    38.   reg En;
    39.   wire [3:0]Y3;
    40. [COLOR="RoyalBlue"] wire [3:0]Y2;  //addition
    41.   wire [3:0]Y1;  //addition[/COLOR]
    42.  
    43.  
    44.     four_to_one fourMux(Y3,A,B,C,D,Sel,En);
    45.         initial
    46.             begin
    47.                 A<=4'b1111;
    48.                 B<=4'b1010;
    49.                 C<=4'b1100;
    50.                 D<=4'b0011;
    51.                 En<=1;
    52.  
    53.                     Sel=00;
    54.                 #20 Sel=01;
    55.                 #20 Sel=10;
    56.                 #20 Sel=11;
    57.                 #20 $finish;
    58.             end
    59.  
    60. endmodule
    61.  
    62.  
     
  16. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Ooops, sorry declare them as "wire"
     
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  17. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Thanks a lot. It does work now.

    Regards
    PG
     
  18. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    Hi again

    I have written the following code for a full adder but it gives an error. The error is about line #13 and says that "Lval 'w1' cannot be a net". Could you please help me with it? Thanks.


    Code ( (Unknown Language)):
    1.  
    2. //full adder
    3.  
    4. module full_adder(S,C_out,A,B,C_in);
    5.  
    6.     input A, B, C_in;
    7.     output S, C_out;
    8.     reg S, C_out;
    9.  
    10.     wire w1;
    11.  
    12.     always @(A or B or C_in)
    13.         begin
    14.             [COLOR="DarkOrange"]assign w1 = A^B;[/COLOR]   //line #13
    15.             assign S = w1^C_in;
    16.             assign C_out = (w1 & C_in) | (A & B);
    17.         end
    18.  
    19. endmodule
    20.  
    21.  
     
    Last edited: Apr 16, 2014
  19. PG1995

    Thread Starter Active Member

    Apr 15, 2011
    753
    5
    UPDATE:
    Thanks for giving it a look. I have fixed it.
     
  20. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    You had the opposite issue, eh? Just remember, if a signal is assigned within a procedural block, as in the always@ block in your first example, then declare it as "register" If a signal connects to a sub-module or is assigned as a concurrent assignment (using "assign") then declare is as "wire" BTW, you code created unintended latches (very bad) Look up intended latches in Verilog(VHDL) Try google eg. unintended+latch+verilog
     
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