I have a Verilog program I need to design of which I orginally posted here, but I thought since I've made progress to repost it.

In short, I have to make an 8-bit wide 2 to 1 multiplexer in Verliog. I think that I have done it using assignments in the module, but we are going to have to use procedural statements to write things in the future and so I'm trying to rewrite it that way. Here is what I am starting with:

module practice_mux2 (SW,LEDR,LEDG);

	input [17:0]SW;
	output[17:0]LEDR;
	output[7:0]LEDG;
	
	assign LEDG[0]=(~SW[17]&SW[0])|(SW[17]&SW[8]);
	assign LEDG[1]=(~SW[17]&SW[1])|(SW[17]&SW[9]);
	assign LEDG[2]=(~SW[17]&SW[2])|(SW[17]&SW[10]);
	assign LEDG[3]=(~SW[17]&SW[3])|(SW[17]&SW[11]);
	assign LEDG[4]=(~SW[17]&SW[4])|(SW[17]&SW[12]);
	assign LEDG[5]=(~SW[17]&SW[5])|(SW[17]&SW[13]);
	assign LEDG[6]=(~SW[17]&SW[6])|(SW[17]&SW[14]);
	assign LEDG[7]=(~SW[17]&SW[7])|(SW[17]&SW[15]);
	
	assign LEDR=SW;
	
endmodule

Can anyone help get me started rewriting this using procedural statement? Thank you in advance.

 

I was able to simplify it to this, but I still can't figure out how to write it in a procedural way.

module practicemux2 (SW,LEDR,LEDG);

	input [17:0]SW;
	output [17:0]LEDR;
	output [7:0]LEDG;
	
	assign LEDG[7:0] = (~SW[17]&SW[7:0])|(SW[17]&SW[15:8]);

	assign LEDR=SW;
	
	 
endmodule