Verilog Syntax error

Discussion in 'The Projects Forum' started by sirius3, Jun 7, 2013.

  1. sirius3

    Thread Starter New Member

    May 30, 2013
    5
    0
    I am using iverilog simulator for mac and when i run the file with extension .va, it says there is a syntax error for the statement " `include discipline.h " The header file is in the same folder. This syntax runs normally otherwise. Could someone please help me out?
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    `include "discipline.h" Notice the quotation marks.
     
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