Verilog - Separating bits for case statement

Discussion in 'Homework Help' started by tquiva, Oct 26, 2012.

  1. tquiva

    Thread Starter Member

    Oct 19, 2010
    176
    1
    My goal is to connect two modules together: RfileReceiver and RegFile
    I did this by implementing a top level module to create instances for these modules. Below is a block diagram of the two modules.

    [​IMG]

    The arrow pointing into RfileReceiver is a 7-bit output called "link" coming from another module. Below is the description of link's bits:

    link[6]: starting bit
    link[5] & link[4]: address
    link[3],link[2],link[1],link[0]: data

    I have the verilog code for modules RegFile and toplevel. My only question here is, how would I go about seperating the bits of the link input into RfileReceiver to accomplish the above description?

    My idea right now is using a case statement. However, I do not know how to represent the particular bits for a given case. For instance, if link = 1011100, I would have:

    case(link)
    begin
    link[5] & link[4]: address
    link[3],link[2],link[1],link[0]: data
    endcase

    I tried googling for the correct Verilog syntax to represent the pseudocode above, but I can't seem to find a solution. Will someone please help me?
     
  2. panic mode

    Senior Member

    Oct 10, 2011
    1,320
    304
    logic start_bit;
    logic [1:0] address;
    logic [3:0] data;

    assign start_bit=link[6];
    assign address=link[5:4];
    assign data=link[3:0];
     
  3. tquiva

    Thread Starter Member

    Oct 19, 2010
    176
    1
    Thank you so much!

    Will someone please take a look at my code? Please let me know if I am missing anything. I'm still kind of new to Verilog.

    Code ( (Unknown Language)):
    1. // Let RfileReceiver = A and RegFile = B
    2.  
    3. // Register file that has four 4-bit registers
    4.  
    5.  
    6. module RegFile(rfdata,clock,waddr,rfaddr,wdata,write);
    7.  
    8. output [3:0] rfdata;  // read data
    9. input clock;
    10. input [1:0] waddrB;  // write address
    11. input [1:0] rfaddrB; // read address
    12. input [3:0] wdataB;  // write data
    13. input writeB;        // write enable
    14.  
    15.  
    16. reg [3:0] regcell[0:3]; // Register array that's 4-bits wide
    17.  
    18. assign rfdata = regcell[rfaddrB]; // Output read data
    19.  
    20. always @(posedge clock)  // Write to the register file
    21.    if (writeB==1) regcell[waddrB]=wdataB;
    22.  
    23.  
    24. endmodule
    25.  
    26.  
    27.  
    28. //-------------------------------------------------------------------------
    29.  
    30. // RfileReceiver circuit
    31. // Assignment is to design this module.  
    32.  
    33. module RfileReceiver(waddr,wdata,write,clock,link,clear);
    34.  
    35. output [1:0] waddrA; // used to control register file
    36. output [3:0] wdataA; // used to tranfer data to register file
    37. output writeA;      // write enable to register file
    38. input  clock;
    39. input  link;        // input from serial link from transmitter
    40. input  clear;
    41.  
    42. assign waddrA = link[5:4];
    43. assign wdataA = link[3:0];
    44.  
    45. always @(posedge clock)
    46.     if (clear != 0) writeA <= 1;
    47.  
    48. endmodule
    49.  
    50. // Top level module to create instances for RfileReceiver and RegFile
    51. // This will connect outputs of RfileReceiver to inputs of RegFile
    52. module toplevel;
    53.  
    54. wire waddrA_waddrB; // Wire from waddrA to waddrB
    55. wire wdataA_wdataB; // wire from wdataA to wdataB
    56. wire writeA_writeB; // wire from writeA to writeB
    57.  
    58. RfileReceiver Rfilereceiver_instance(
    59.     .waddrA(waddrA_waddrB),
    60.     .wdataA(wdataA_wdataB),
    61.     .writeA(writeA_writeB)
    62.     );
    63.    
    64. RegFile RegFile_instance(
    65.     .waddrB(waddrA_waddrB),
    66.     .wdataB(wdataA_wdataB),
    67.     .writeB(writeA_writeB)
    68.     );
    69.    
    70. endmodule
    71.  
    72.  
     
  4. panic mode

    Senior Member

    Oct 10, 2011
    1,320
    304
    first of all what language version you use? verilog-1995, verilog-2001 or SystemVerilog-2005? they are different, I only used SystemVerilog-2005 so your syntax looks odd to me.

    did you try to compile it? what kind of errors do you get?

    the way i see it, your module declaration is incorrect so this probably cannot compile.

    also your code does not match signals in the block diagram. in the diagram you have one input whcih is not labeled (presumably 'link') and three outputs: 'waddr', 'wdata', 'write'. your code however seem to use bunch of inputs and only output is rfdata. for me this alone is good enough reason to not even look any further, as this need to be addressed frst.
     
    Last edited: Oct 27, 2012
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