Verilog question

Discussion in 'Programmer's Corner' started by Joe24, Sep 23, 2008.

  1. Joe24

    Thread Starter Active Member

    May 18, 2007
    52
    0
    Hello,

    Ok, I have a piece of Verilog code that I want to use. But somethings are unclear to me. For example, consider the following small piece of code:

    parameter x = 5000;

    wire [16:0] y = (x << 20);

    Ok, so this is a simple example code that illustrates my question. Question is:
    How is x shifted to the left by 20? Would I have to convert 5000 from decimal to bits and shift left by 20 bit positions?

    Thanks
     
  2. roddefig

    Active Member

    Apr 29, 2008
    149
    0
    Yes. However, you'll end up with all zeroes as your data type is only 17 bits wide.
     
  3. Joe24

    Thread Starter Active Member

    May 18, 2007
    52
    0
    So the compiler I guess would automatically convert from decimal to binary?
    Where in contrast, in VHDL, we the programmers would have to explicitly force the conversion in the code. Ex.

    Singal X: Integer range 0 to 256;
    Signal Y: std_logic_vector( 7 downto 0);
    .
    . // somwhere in between y gets assigned some binary value
    .
    x <= to_integer( y);


    RIght??
     
  4. roddefig

    Active Member

    Apr 29, 2008
    149
    0
    I'm not really familiar with VHDL, but I don't think it should matter. The actual representation of the number in FPGA is always binary (signed or unsigned).
     
Loading...