Verilog project help

Discussion in 'The Projects Forum' started by sdm320, Dec 10, 2011.

  1. sdm320

    Thread Starter New Member

    Dec 10, 2011
    1
    0
    The problem statement for the project is:
    Your are to build and control a Functional Unit (FU) based on the C program below. The FU has to handle 8 bit negative numbers and does the following operations: 1 power operation A^B note that B cannot be negative. 2 it can do addition of two numbers. 3 it can do bitwise OR operation.

    C program is as follows:

    Code ( (Unknown Language)):
    1.  
    2. void problem3_4()
    3. {
    4. int i;
    5. int count;
    6. int sum; //must be shown on a seven segment display
    7. /*these values can be considered inputs. To test your program make these values parameters and set them to 4, but make your design robust enough to handle other values*/
    8. int max1;//this is an unknown value that happens at runtime
    9.  
    10. sum = 1;
    11. for(i=1;i<max1;i++)
    12. {
    13. //depending on what state the FU is in one of these three operations will //happen
    14. sum=sum^i;
    15. sum=sum+i;
    16. sum=sum|0x80;
    17. }
    18. }
    19.  
    20.  
    21.  
    22. Here is what I have so far:
    23.  
    24. module Lab7(clk, reset, enA, enB, enC, s, ctl, in1, displayOut1, displayOut2, displayOut3);
    25. input [3:0]in1;
    26. input [1:0]ctl;
    27. input clk;
    28. input reset;
    29. input enA;
    30. input enB;
    31. input enC;
    32. input s;
    33. wire [3:0]aluOut;
    34. output [6:0] displayOut1, displayOut2, displayOut3;
    35. wire clk, reset, enA, enB, enC, s;
    36. wire [3:0] in1;
    37. wire [1:0]ctl;
    38. wire [6:0] displayOut1, displayOut2, displayOut3;
    39. wire[3:0] temp_displayOut1;
    40. wire [3:0] temp_displayOut2;
    41. wire[3:0] temp_displayOut3;
    42. wire[3:0] temp_inB;
    43. Mux mux1(in1, temp_displayOut3, temp_inB);
    44. Reg reg_a(clk, in1, reset, enC, temp_displayOut1);
    45. Reg reg_b(clk,temp_inB, resest, enC, temp_displayOut2);
    46. Reg reg_c(clk, outAlu,reset,enC,temp_displayOut3);
    47. alu alu_1(s, reg_a, reg_b, aluOut);
    48.  
    49. SevenSegmentDisplayDecoder a1(displayOut1,temp_displayOut1);
    50. SevenSegmentDisplayDecoder a2(displayOut2,temp_displayOut2);
    51. SevenSegmentDisplayDecoder a3(displayOut3,temp_displayOut3);
    52.  
    53. endmodule
    54.  
    55.  
    56. module alu(a, b, ctl_1, outAlu);
    57.  
    58.  input [7:0] a;
    59.  input [7:0] b;         // port A,B
    60.  output [3:0] outAlu;        // the result
    61.  input [1:0] ctl_1;        // functionality control for ALU
    62.  wire ctl_1;
    63.  wire [3:0]a;
    64.  wire [3:0]b;
    65.  reg [3:0]outAlu;  
    66.    
    67.  always@(ctl_1 or a or b)
    68.  begin
    69.  case (ctl_1)
    70. 2'b00: outAlu <= a&b;
    71. 2'b01: outAlu <= a|b;
    72. 2'b10: outAlu <= a+b;
    73. 2'b11: outAlu <= a-b;
    74. endcase
    75. end
    76.  
    77. endmodule
    78.  
    79. module SevenSegmentDisplayDecoder(ssOut, nIn);
    80.   output reg [6:0] ssOut;
    81.   input [3:0] nIn;
    82.  
    83.   // ssOut format {g, f, e, d, c, b, a}
    84.  
    85.   always @(nIn)
    86.     begin
    87.     case (nIn)
    88.       4'h0: ssOut = 7'b0111111;
    89.       4'h1: ssOut = 7'b0000110;
    90.       4'h2: ssOut = 7'b1011011;
    91.       4'h3: ssOut = 7'b1001111;
    92.       4'h4: ssOut = 7'b1100110;
    93.       4'h5: ssOut = 7'b1101101;
    94.       4'h6: ssOut = 7'b1111101;
    95.       4'h7: ssOut = 7'b0000111;
    96.       4'h8: ssOut = 7'b1111111;
    97.       4'h9: ssOut = 7'b1100111;
    98.       4'hA: ssOut = 7'b1110111;
    99.       4'hB: ssOut = 7'b1111100;
    100.       4'hC: ssOut = 7'b0111001;
    101.       4'hD: ssOut = 7'b1011110;
    102.       4'hE: ssOut = 7'b1111001;
    103.       4'hF: ssOut = 7'b1110001;
    104.       default: ssOut = 7'b1001001;
    105.     endcase
    106.     ssOut = ~ssOut;
    107.     end
    108. endmodule
    109.  
    110.  
    111. module Reg (clk, in, reset, en, out);
    112. input [3:0] in;
    113. input clk;
    114. input reset;
    115. input en;
    116. reg out;
    117. output [3:0]out;
    118. always @ (posedge clk or negedge reset)
    119. begin
    120. if (reset == 1'b0)
    121. out = 4'b0000;
    122. else
    123. begin
    124.    if(en==1'b1)
    125.    out = in;
    126.    end
    127.   end
    128. endmodule
    129.  
    130. module Mux(s,d, b, e);
    131.  
    132. input [7:0]d;
    133. input [7:0]b;
    134. input s;
    135. output [3:0]e;
    136. wire s;
    137. wire [3:0]d;
    138. wire [3:0]b;
    139. reg e;
    140. always @(s or d or b or e)
    141. begin
    142. if(s==1'b0)
    143. e=d;
    144. else
    145. e=b;
    146. end
    147.  
    148. endmodule
    149.  
    150.  
    I'm not sure how to implement the state machine, handle negative numbers (I think twos complement), and the power function.
     
    Last edited by a moderator: Dec 11, 2011
Loading...