In you testbench, at the initial block, you can try this:

force jk0.q = 0;
#10 ( or whatever)
release jk0.g;

If it works, then making a reset will fix your problem

 

FWIW, If the OP had tried what I suggested, he would have had this working very quickly.

You can lead a horse to water, but you can't make it drink.

 module jkff (q, j, k, clk, rst);
 input rst;
 input j, k, clk;
 output q;
 wire clkn, g1o, g2o, g5o, g6o, qn, rst;
 not n1(clkn, clk);
 nand g1(g1o, j, clk, qn);
 nand g2(g2o, k, clk, q);
 nand g3(s, r, g1o, rst);
 nand g4(r, s, g2o);
 nand g5(g5o, s, clkn, rst);
 nand g6(g6o, r, clkn);
 nand g7(q, qn, g5o);
 nand g8(qn, q, g6o);
 endmodule

 module tb;
    reg j, k, clk, rst;
    wire q;
    jkff jk0(q, j, k, clk, rst);
    initial begin
        rst = 0;
 clk = 0;
        #20
        rst = 1;
        j = 0;
        k = 1;
        #100
        clk = 1;
        #20
        clk = 0;
        #20
        clk = 1;
     end
 endmodule