Discussion in 'Programmer's Corner' started by Bobsons, Aug 21, 2014.

1. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
Hi all.
I really need help with Verilog.
Our lecturer has restricted to use if/else and etc.. We are allowed to use just AND OR NOT and etc logic gates.
We are also restricted to use counters like n = n + 1 and supposed to make it with flip-flops

The Prime Number
A prime number (or a prime) is a natural number greater than 1 that has
no positive divisors other than 1 and itself. A natural number greater than
1 that is not a prime number is called a composite number. For example, 5
is prime because 1 and 5 are its only positive integer factors, whereas 6 is
composite because it has the divisors 2 and 3 in addition to 1 and 6.
In this assignment, on the Verilog environment, you will design a prime
counter counting between 1-63 and repeating 5 times by returning to the
beginning. Your each code line must include an explanation line, and another
something important is that your codes must be synthesizable.

Im stuck at making counters because dont know Verilog well
My code is:
Code ( (Unknown Language)):
1.
2. module dff (Q,D, CK);
3.     input CK,D;
4.     output Q;
5.
6.     wire NM,NCK;
7.     wire NQ,M;
8.
9. nand DN1 (NM,D,CK);
10. nand DN2 (M,NM,CK);
11. nand DN3 (Q,NQ,NM);
12. nand ND4 (QN,Q,M);
13. endmodule
14.
15. module tb;
16.     reg D, CK;
17.     wire Q;
18.     dff p0(Q, D, CK);
19.     //jkstruct m0(q, qn, t, cp);
20.     initial begin
21.         D = 0;
22.         CK = 1;
23.         #100;
24.         \$display(Q);
25.         D = 0;
26.         CK = 1;
27.         #50
28.         \$display(Q);
29.         D = 1;
30.         CK = 0;
31.         #50
32.         \$display(Q);
33.         D = 1;
34.         CK = 1;
35.
36.         \$display(Q);
37.         \$finish;
38.     end
39. endmodule

I cant even test my flip flop...

2. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
This is why you shouldn't wait until the project is nearly due before you start asking questions - ask them often and as soon as there is any confusion.

Why can't you test your flip flop?

3. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
Well I have done all minor modules. just counter left. The problem is that I actually dont understand how to represent it in code. But I have build it on chips with wires and LEDs.

I need a counter with reset on verilog. The modules must be done with logic gates. This is the problem for me
I always get X from Q output... Whatever I do I get x

Last edited: Aug 21, 2014
4. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Code (Text):
1. module dff (Q,D, CK);
2.     input CK,D;
3.     output Q;
4.
5.     wire NM,NCK;
6.     wire NQ,M;
7.
8. nand DN1 (NM,D,CK);
9. nand DN2 (M,NM,CK);
10. nand DN3 (Q,NQ,NM);
11. nand ND4 (QN,Q,M);
12. endmodule
The X means you have undefined signals at some point. Initializing values can help...

Use an always block that makes Q <= D on each rising edge of the clock.

5. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
That is the problem. We are restricted to use always, <= , and etc in the modules.

6. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Restricted to use means you can only use them - you seem to mean restricted from use.

Are you sure this is the case in regards to the flip flop design? I can understand it at the counter level, but not the flip flop level.

Why don't you list everything you can't use instead of telling us after the fact?

7. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
Our lecturer said that we are restricted to design the cirquit with if/else <= loops, and all the other high level programming ways.
When I asked him the list of restrictions - he said "estricted to design the cirquit with if/else <= loops, and all the other high level programming ways." and left the class. When I went his office - he said same without any details...
He just said to use logic gates otherwise we get 0 points...

8. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
I just need to make this flip flop to work. Im getting X as output. But how to set default value to reg without <=?

9. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
In your testbench, make sure you put
Code ( (Unknown Language)):
1. initial
2.    begin
3.     D =0;
4.     end

10. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
Done already. Not helped. Output is always X

11. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Okay, have a look at your flip flop code. Draw it out from the Verilog. You'll find that NQ is not defined, yet is an input to a NAND gate... Your output cannot be determined because you have an indeterminate input.

Last edited: Aug 22, 2014
12. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Take a look at this, it shows how you can implement a D flip flop...

Last edited: Aug 22, 2014
13. ### Brownout Well-Known Member

Jan 10, 2012
2,375
998
Try this:

NOT N1(NQ, D)
...
NAND DN2(M, NQ, CK)
NAND DN3(Q, QN, NM)
NAND DN4(QN, Q, M)

14. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0

Thying to implement a JK flip-flop in Verilog but always get X output. My head is going to explode...
Code:
Code ( (Unknown Language)):
1.
2. module jkff (q, j, k, clk);
3.     input j, k, clk;
4.     output q;
5.     wire clkn, g1o, g2o, g5o, g6o, qn;
6.
7.     not n1(clkn, clk);
8.
9.     nand g1(g1o, j, clk, qn);
10.     nand g2(g2o, k, clk, q);
11.
12.     nand g3(s, r, g1o);
13.     nand g4(r, s, g2o);
14.
15.     nand g5(g5o, s, clkn);
16.     nand g6(g6o, r, clkn);
17.
18.     nand g7(q, qn, g5o);
19.     nand g8(qn, q, g6o);
20. endmodule
21.
And a TestBench:
Code ( (Unknown Language)):
1. module tb;
2.     reg j, k, clk;
3.     wire q;
4.     jkff jk0(q, j, k, clk);
5.     initial begin
6.         j = 1;
7.         k = 0;
8.         #100
9.         clk = 1;
10.         #20
11.         clk = 0;
12.         #20
13.         clk = 1;
14.
15.     end
16.
17. endmodule
Used this picture to write code: http://www.indiabix.com/_files/images/electronics-circuits/jk-flip-flop.png

The problem is in
Code ( (Unknown Language)):
1. nand g7(q, qn, g5o);
2.     nand g8(qn, q, g6o);

Last edited: Aug 23, 2014
15. ### Brownout Well-Known Member

Jan 10, 2012
2,375
998
Try initializing clk to zero and make sure you declare r and s.

16. ### Brownout Well-Known Member

Jan 10, 2012
2,375
998
Oh, one more thing. Your flip-flop will start in an unknown state. You need a way to set or reset it to a known state.

Add a reset wire to g4 and g8.

17. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
How to? Im newbie in Verilog....

18. ### Brownout Well-Known Member

Jan 10, 2012
2,375
998
Just make new ports for reset like you have for clk and d. Connect to the inputs like the other signals.

19. ### Bobsons Thread Starter New Member

Aug 21, 2014
9
0
The problem is that I dont know why it is not working. New data is not assigning to FF at all

20. ### Brownout Well-Known Member

Jan 10, 2012
2,375
998
I can only suggest ways to get it to work. You have to try to implement them. Or not if you want to continue to flounder.