Verilog HELP

Discussion in 'Programmer's Corner' started by satishsa, Jan 7, 2012.

  1. satishsa

    Thread Starter New Member

    Jan 7, 2012
    1
    0
    I am trying to model a block and am writing behavioural verilog. I am using Icarus Verilog v0.9 to compile but i keep getting syntax error on line 43:

    Any idea why this is? This seems like a legitimate line of code to me

    Code ( (Unknown Language)):
    1.  
    2. `timescale 1ps/1ps
    3.  
    4. module unb_bfm (iUNB_ENABLE,
    5.         iREFCLK,
    6.         oDB_DATA,
    7.         oDB_CLK,
    8.         oDB_VALID);
    9.  
    10. input iUNB_ENABLE;
    11. input iREFCLK;
    12. output [1:0] oDB_DATA;
    13. output oDB_CLK;
    14. output oDB_VALID;
    15.  
    16. reg db_clk;
    17. reg db_data_valid;
    18. reg [1:0] db_data;
    19.  
    20. //wire m_value;
    21. //wire n_value;
    22. reg count_done;
    23. reg count_m_done;
    24. reg count_n_done;
    25. reg db_clk_trigger;
    26. reg db_data_trigger;
    27. integer i;
    28.  
    29. parameter HALF_PERIOD = 667; // Approximately 750 MHz
    30. parameter M_VALUE = 2;
    31. parameter N_VALUE = 2;
    32.  
    33. initial begin
    34.     db_clk = 1'b0;
    35.     db_data_valid = 1'b0;
    36.     db_data = 2'b00;
    37.     count_done = 1'b0;
    38.     count_m_done = 1'b0;
    39.     count_n_done = 1'b0;
    40.     db_clk_trigger = 1'b0;
    41.     db_data_trigger = 1'b0;
    42. end
    43.  
    44. while (iUNB_ENABLE==1) begin  // <--------- this is line 43.
    45.     db_clk_trigger = 1'b1;
    46.  
    47.  
     
    Last edited by a moderator: Jan 13, 2012
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    I am not skilled in verilog, but posting the exact wording of that syntax error could help.
     
  3. guitarguy12387

    Active Member

    Apr 10, 2008
    359
    12
    This seems pretty strange to me. Looks like this code is written for a testbench... but you don't have any UUT and your TB has ports (which I can't imagine a reason for).

    If you didn't intend this to be a testbench, you need to re-think this. It is not synthesizable. I get the sense there is more to this code than you are showing. Also, please use the 'code' tags.

    As kubeek said, seeing the exact error message would help
     
  4. abettino

    New Member

    Jan 12, 2012
    4
    0
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    You can only use structures like "while" "for", etc in a sequential block. You need to define an "always @" and then use a clock in the sensitivity list or else a wait statement inside the sequential block. Look up the definition of "always @" and read on sequential blocks. You may also use "initial" for code that executes only once.
     
  6. abettino

    New Member

    Jan 12, 2012
    4
    0
    Ah yeah Brownout you are definitely right. Those need to be wrapped in an initial block or always block.
     
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