I have been working at this code for hours now and can't seem to figure out my mistake. Essentially, the code acts as a 4-bit binary to BCD converter. After the final value of each digit has been determined, it is sent to a module to print it out on a 7-segment display using cathode and anode. Behaviorally, the modules work fine. However, once translated, the code breaks down. A post-translation simulation reveals that "state" from the main module is being recognized as a 3-bit array, instead of 2. Any and all help is greatly appreciated.
Here is the main module
Here is the main module
Rich (BB code):
module Binary_Display
(input CLK_50M,
input [7:0] switches,
input reset,
output [6:0] cathode,
output [3:0] anode);
parameter [1:0] CLEAR = 2'b00,
SHIFT = 2'b01,
ADD_3 = 2'b10;
wire mili_clk;
reg [1:0] state, next = 0;
reg [7:0] switch_temp, binary;
reg [3:0] hundreds, tens, ones, hfinal, tfinal, ofinal;
reg [3:0] shift_counter;
Top_Module clock
(.CLK_50M(CLK_50M),
.reset(reset),
.Milli_sec_clock(mili_clk));
Display control
(.clk_mili(mili_clk),
.hundreds(hfinal),
.tens(tfinal),
.ones(ofinal),
.reset(reset),
.anode(anode),
.cathode(cathode));
always @ (posedge CLK_50M or posedge reset) begin
if (reset) begin
state <= CLEAR;
end else if (switch_temp != switches) begin
state <= CLEAR;
end else begin
state <= next;
end
end
always @* begin
next = state;
case (state)
CLEAR: begin
switch_temp = switches;
shift_counter = 0;
hundreds = 0;
tens = 0;
ones = 0;
binary = switches;
next = SHIFT;
end
SHIFT: begin
hundreds = {hundreds[2:0], tens[3]};
tens = {tens[2:0], ones[3]};
ones = {ones[2:0], binary[7]};
binary = {binary[6:0], 1'b0};
shift_counter = shift_counter + 1;
next = ADD_3;
end
ADD_3: begin
if (shift_counter == 8) begin
hfinal = hundreds;
tfinal = tens;
ofinal = ones;
next = CLEAR;
end
else begin
if (hundreds > 4) begin
hundreds = hundreds + 3;
end
if (tens > 4) begin
tens = tens + 3;
end
if (ones > 4) begin
ones = ones + 3;
end
next = SHIFT;
end
end
default: next = CLEAR;
endcase
end
endmodule
here is the module for determining cathode and anode
module Display
(input clk_mili,
input [3:0] hundreds,
input [3:0] tens,
input [3:0] ones,
input reset,
output reg [3:0] anode,
output reg [6:0] cathode);
parameter [2:0] state1 = 3'b000,
state2 = 3'b001,
state3 = 3'b010,
state4 = 3'b011,
state5 = 3'b100;
reg [2:0] state, next;
reg [3:0] T1;
reg [6:0] temp1;
always@ (posedge clk_mili or posedge reset) begin
if (reset) begin
state <= state1;
end else begin
state <= next;
end
end
always@ * begin
case (state)
state1: begin
cathode = 1;
anode = 0;
next = state2;
end
state2: begin
anode = 4'b1110;
T1 = ones;
case (T1)
0: temp1 = 7'b0000001;
1: temp1 = 7'b1001111;
2: temp1 = 7'b0010010;
3: temp1 = 7'b0000110;
4: temp1 = 7'b1001100;
5: temp1 = 7'b0100100;
6: temp1 = 7'b0100000;
7: temp1 = 7'b0001111;
8: temp1 = 7'b0000000;
9: temp1 = 7'b0000100;
10: temp1 = 7'b0001000;
11: temp1 = 7'b1100000;
12: temp1 = 7'b0110001;
13: temp1 = 7'b1000010;
14: temp1 = 7'b0110000;
15: temp1 = 7'b0111000;
endcase
cathode = temp1;
next = state3;
end
state3: begin
anode = 4'b1101;
T1 = tens;
case (T1)
0: temp1 = 7'b0000001;
1: temp1 = 7'b1001111;
2: temp1 = 7'b0010010;
3: temp1 = 7'b0000110;
4: temp1 = 7'b1001100;
5: temp1 = 7'b0100100;
6: temp1 = 7'b0100000;
7: temp1 = 7'b0001111;
8: temp1 = 7'b0000000;
9: temp1 = 7'b0000100;
10: temp1 = 7'b0001000;
11: temp1 = 7'b1100000;
12: temp1 = 7'b0110001;
13: temp1 = 7'b1000010;
14: temp1 = 7'b0110000;
15: temp1 = 7'b0111000;
endcase
cathode = temp1;
next = state4;
end
state4: begin
anode = 4'b1011;
T1 = hundreds;
case (T1)
0: temp1 = 7'b0000001;
1: temp1 = 7'b1001111;
2: temp1 = 7'b0010010;
3: temp1 = 7'b0000110;
4: temp1 = 7'b1001100;
5: temp1 = 7'b0100100;
6: temp1 = 7'b0100000;
7: temp1 = 7'b0001111;
8: temp1 = 7'b0000000;
9: temp1 = 7'b0000100;
10: temp1 = 7'b0001000;
11: temp1 = 7'b1100000;
12: temp1 = 7'b0110001;
13: temp1 = 7'b1000010;
14: temp1 = 7'b0110000;
15: temp1 = 7'b0111000;
endcase
cathode = temp1;
next = state5;
end
state5: begin
anode = 4'b0111;
cathode = 1;
next = state2;
end
3'b101: next = state1;
3'b110: next = state1;
3'b111: next = state1;
default: next = state1;
endcase
end
endmodule
and finally, here is a module that is used to generate a 1 millisecond clock
module Top_Module
(input CLK_50M,
input reset,
output reg Milli_sec_clock);
reg [14:0] counter = 0;
always @ (posedge CLK_50M or posedge reset) begin
if (reset) begin
Milli_sec_clock <= 0;
counter <= 1;
end else begin
if (counter == 25000) begin
Milli_sec_clock <= ~Milli_sec_clock;
counter <= 1;
end else if (counter == 0) begin
Milli_sec_clock <= 0;
counter <= 1;
end else begin
counter <= counter + 1;
end
end
end
endmodule
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