Verilog Help

Discussion in 'Programmer's Corner' started by Chippo, Oct 2, 2011.

  1. Chippo

    Thread Starter New Member

    Oct 2, 2011
    2
    0
    Hi

    I would consider myself a novice in verilog. So here is the code that my teacher gave us for an unsigned multiplier, but I can't seem to get an output from it. Can anyone help? I wrote a testbench to test different inputs and get nothing for the output. I am trying to instantiate this in a 5x5 signed multiplier for the project, but his code isn't working. Here's the code:

    Code ( (Unknown Language)):
    1.  
    2. module mult4x4(clk, st, mplier, mcand, prod, done);
    3.     input clk;
    4.     input st;
    5.     input [3:0] mplier, mcand;
    6.     output [8:0] prod; //added
    7.     output done;
    8.  
    9.    reg done;
    10.    reg [3:0] pstate,nstate;
    11.    reg [8:0] prod;
    12.  
    13.    parameter s0=4'b0000, s1=4'b0001, s2=4'b0010, s3=4'b0011;
    14.    parameter s4=4'b0100, s5=4'b0101, s6=4'b0110, s7=4'b0111;
    15.    parameter s8=4'b1000, s9=4'b1001;
    16.  
    17.     reg [8:0] ACC; //accumulator
    18.     //reg M=ACC[0]; //M is bit 0 of ACC; could use 'define
    19.     wire M;
    20.    
    21.     assign M = ACC[0];
    22.  
    23.     always @(posedge clk or posedge st)
    24.        if (st) pstate = s0;
    25.        else pstate = nstate;
    26.  
    27.     always @(pstate) //state transition
    28.         case (pstate)
    29.           s0: if(st) nstate = s1;
    30.           s1: if (M) nstate = s2; else nstate = s3;
    31.           s2: nstate = s3;
    32.           s3: if (M) nstate = s4; else nstate = s5;
    33.           s4: nstate = s5;
    34.           s5: if (M) nstate = s6; else nstate = s7;
    35.           s6: nstate = s7;
    36.           s7: if (M) nstate = s8; else nstate = s9;
    37.           s8: nstate = s9;
    38.           s9: nstate = s0;
    39.         endcase
    40.  
    41.      always @(pstate) //Output (Action)
    42.         case (pstate)
    43.          s0: begin
    44.               ACC[8:4] = 5'b00000;
    45.               ACC[3:0] = mplier;
    46.               end
    47.          s1: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
    48.          s2: ACC = {1'b0, ACC[8:1]};
    49.          s3: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
    50.          s4: ACC = {1'b0, ACC[8:1]};
    51.          s5: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
    52.          s6: ACC = {1'b0, ACC[8:1]};
    53.          s7: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
    54.          s8: ACC = {1'b0, ACC[8:1]};
    55.          s9: begin
    56.               done = 1'b1;
    57.               prod = ACC;
    58.               end
    59.       endcase
    60. endmodule
    61.  
     
    Last edited: Oct 2, 2011
  2. ajm113

    Member

    Feb 19, 2011
    176
    5
    Hello and weclome to the forums Chippo!

    If I may give a word of advice on posting code, can you please use the [ code ] [ /code]tags around your source code? It makes reading source code a little easier for others with formatting included. :)

    Thank you!
     
  3. Chippo

    Thread Starter New Member

    Oct 2, 2011
    2
    0
    Hey,

    I did it now. Sorry about that.
     
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