Verilog Help please

Discussion in 'Programmer's Corner' started by rishid, Aug 1, 2006.

  1. rishid

    Thread Starter New Member

    Oct 24, 2005
    8
    0
    Hi,

    First verilog app I have writen. It is pretty simple assignment, except I cannot get it to work. :rolleyes:
    Basically 2 inputs, datain [7:0] and a avail, and 2 outputs largest [7:0] and ready.

    When avail changes from 0 to 1, largest reg should be reset. Then while avail is 1, any datain should be compared to the largest reg and saved if it is greater than the value in the register. Then once avail becomes 0, ready should become 1.

    Anyone have any ideas on what is wrong below? My largest reg is always outputting X's

    Thanks,

    Rishi


    Code ( (Unknown Language)):
    1.  
    2. module comp_datapath (input [7:0] datain, input avail, output reg [7:0] largest);
    3.  initial begin
    4.   largest = 0;
    5.  end
    6.  always @(avail, datain) begin
    7.   if (avail) begin  
    8.    if (datain > largest) largest = datain;
    9.   end
    10.  end
    11. endmodule
    12. module comp_controller (input avail, output ready);
    13.  assign ready = avail ? 0 : 1;
    14. endmodule
    15.  
     
  2. BrunoEE

    New Member

    Sep 6, 2006
    5
    0
    Please post your test bench and I should easily be able to help you! There is a couple of things that could be going wrong here.
     
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