Verilog HDL - Conversion of 16-Bit Float to Real

Discussion in 'Programmer's Corner' started by vjabagch, Jul 23, 2009.

  1. vjabagch

    Thread Starter New Member

    Jul 23, 2009
    4
    0
    I have a Sine Cosine ROM module which I generated from Matlab using a half-precision function available from the Matlab site. It consists of a 10 bit address space and a 16-bit data bus.

    I have a test bench and a unit under test and need to display 16-bit half precision floating point numbers as reals so that I can visually see if my module contains the proper values.



    I am getting extremely large (and incorrect) numbers from the simulation.


    I have pasted an example simulation output.

    # 0.00 radians --> sin = 131072.0000 cos = 1.0000
    # 0.01 radians --> sin = 131072.0000 cos = 1.0000
    # 0.01 radians --> sin = 16777216.0000 cos = 1.0000
    # 0.01 radians --> sin = 16777216.0000 cos = 1.0000

    ...

    # 6.27 radians --> sin = 4261412864.0000 cos = 1.0000
    # 6.27 radians --> sin = 4278190080.0000 cos = 1.0000
    # 6.28 radians --> sin = 4278190080.0000 cos = 1.0000
    # 6.28 radians --> sin = 4294836224.0000 cos = 1.0000

    The testbench contains the main problem inside the monitor statement.

    $monitor ("%1.2f radians --> sin = %1.4f cos = %1.4f", (address * 2 * pi / 1023),
    ((-1)**(sine[15])) * (1'b1 + (sine[9:0] >> 10)) * (2 ** (sine[14:10] - 5'd15)),
    ((-1)**(cosine[15])) * (1'b1 + (cosine[9:0] >> 10)) * (2 ** (cosine[14:10] - 5'd15)) );

    My questions are as follows:

    Is my monitor statement set up correctly to convert from 16-bit floating point to real (x.xxxx format).

    What is the max number of decimal digits that half precision (16 bit floating point) would produce to the right of the decimal point? Since I am dealing with sin and cosine from 0 to 2pi I only need 1 digit to the left.





    I have uploaded my module and test-bench to the following address.

    http://vahejabagchourian.comyr.com/Verilog/

    The individual files are stored at:

    http://vahejabagchourian.comyr.com/Verilog/sync_rom.v
    http://vahejabagchourian.comyr.com/Verilog/sync_rom_tb.v

    Any help is greatly appreciated.

    Thank You,
    Vahe
     
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