verilog confusion

Discussion in 'Programmer's Corner' started by spookymulder, Aug 23, 2014.

  1. spookymulder

    Thread Starter New Member

    Aug 23, 2014
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    Hi everyone. New to the forum as well as pretty much any programming language stuff. Long story short, the question is:

    Write a Verilog module for the circuit F(X,Y)=Y+X'Y' using verilog primitives AND, OR and NOT.

    Took the lecture last semester. Not once did verilog even get mentioned so I'm trying to figure out what I can from my book. Not going so well. Most of the examples I've found out in the web are WAY too complex with very little explanation that makes sense to follow what's going on. This question is then followed up with drawing a timing diagram for the circuit which I think I may be able to figure out but not sure. Any help would be greatly appreciated.
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
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    Look up structural verilog. Also, see the thread about Verilog prime numbers (just above this one) It contains some simple examples.
     
  3. tshuck

    Well-Known Member

    Oct 18, 2012
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  4. spookymulder

    Thread Starter New Member

    Aug 23, 2014
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    thanks tshuck. had a hard time finding simpler examples or better explanation of how this code is supposed to function.
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    If you want to check out the Verilog prime number thread, there is an example now that works (sort of, it's not exactly right, but now the data output pins of J-K flip-flop update correctly)
     
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