Hi everyone. New to the forum as well as pretty much any programming language stuff. Long story short, the question is: Write a Verilog module for the circuit F(X,Y)=Y+X'Y' using verilog primitives AND, OR and NOT. Took the lecture last semester. Not once did verilog even get mentioned so I'm trying to figure out what I can from my book. Not going so well. Most of the examples I've found out in the web are WAY too complex with very little explanation that makes sense to follow what's going on. This question is then followed up with drawing a timing diagram for the circuit which I think I may be able to figure out but not sure. Any help would be greatly appreciated.