verilog code

Discussion in 'General Electronics Chat' started by vead, Sep 14, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    hello,

    I have made sample code for 4 bit ALU and 3 to 8 decoder to make 4 bit processor . as designer we can design anything so I have started to design processor with two function ALU and decoder
    4 bit alu
    Code (Text):
    1. Module alu (a,b,s0,s1,s2 f);
    2. Input a,b,s0,s1,s2;
    3. Output f;
    4. Reg [3:0];
    5. Always @(s0,s1,s2);
    6. Begian
    7. Case (s0,s1,s2);
    8. 3b’000 :f=(a&b);
    9. 3b’001:f= (a|b);
    10. 3b’010 :f= ~(a&b);
    11. 3b’011 :f= ~ (a|b);
    12. 3b’100:f=(a^b);
    13. 3b’101: f=(a*b);
    14. 3b’110: f=(a+b);
    15. 3b’111:f=(a-b );
    16. End case
    17. End module
    3to 8 decoder
    Code (Text):
    1. Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    2. Input a2,a1,a0;
    3. Output d7,d6,d5,d4,d3,d2,d1,d0;
    4. Wire [7:0];
    5. Always @(a2,a1,a0);
    6. Begin
    7. Case (a2,a1,a0);
    8. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    9. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    10. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    11. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    12. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    13. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    14. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    15. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    16. Endcase
    17. Endmodule

    I don't understand how to connect 4 bit Alu with
    3 to 8 bit decoder to make 4 bit processor
     
    Last edited: Sep 14, 2014
  2. tglaria

    New Member

    Aug 11, 2014
    13
    0
    Well, I guess this is posted in the wrong forum.
    Your question is about programming rather than electronics.

    Another thing, you have a typo on your first 'code' "Begian"
    And don't remember if it's "Endcase" or "End case", my verilog is rusted...
     
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