Verilog code wont simulate properly

Discussion in 'Programmer's Corner' started by linux2k, Nov 12, 2009.

  1. linux2k

    Thread Starter New Member

    Dec 13, 2008
    3
    0
    I'm making a behavioral model of BCD to 7-segment decoder. But its does not give the predicted results. The output of all the segments are 'z'.

    Code ( (Unknown Language)):
    1.  
    2. module binaryTo7Seg(code, segment);
    3.  
    4. output reg [7:0] segment;
    5. input [3:0] code;
    6.  
    7. always@(code)
    8. case(code)
    9.        0: segment = ~8'b11111100;  
    10.        1: segment = ~8'b01100000;
    11.        2: segment = ~8'b11011010;
    12.        3: segment = ~8'b11110010;  
    13.        4: segment = ~8'b01100110;  
    14.        5: segment = ~8'b10110110;
    15.        6: segment = ~8'b10111110;
    16.        7: segment = ~8'b11100000;
    17.        8: segment = ~8'b11111110;
    18.        9: segment = ~8'b11100110;
    19.       10: segment = ~8'b11101110;  
    20.       11: segment = ~8'b00111110;
    21.       12: segment = ~8'b10011100;
    22.       13: segment = ~8'b01111010;
    23.       14: segment = ~8'b10011110;
    24.       15: segment = ~8'b10001110;
    25.       default: segment = 8'bx;
    26.     endcase
    27.  
    28. endmodule
    29.  
    Code ( (Unknown Language)):
    1.  
    2. module binaryTo7Seg_test(code, segment);
    3.  
    4. output reg [3:0] code;
    5. input  [7:0] segment;
    6.  
    7. initial
    8.  
    9.       begin
    10.  
    11.          $monitor($time,,,"A = %b B = %b C = %b D = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b, hSeg = %b",code[3],code[2],code[1],code[0],segment[7],segment[6],segment[5],segment[4],segment[3],segment[2],segment[1],segment[0]);
    12.  
    13.          #10  code[3] = 0; code[2] = 0; code[1] = 0; code[0] = 0;
    14.          #10  code[3] = 0; code[2] = 0; code[1] = 0; code[0] = 1;
    15.          #10  code[3] = 0; code[2] = 0; code[1] = 1; code[0] = 0;
    16.          #10  code[3] = 0; code[2] = 0; code[1] = 1; code[0] = 1;
    17.          #10  code[3] = 0; code[2] = 1; code[1] = 0; code[0] = 0;
    18.          #10  code[3] = 0; code[2] = 1; code[1] = 0; code[0] = 1;
    19.          #10  code[3] = 0; code[2] = 1; code[1] = 1; code[0] = 0;
    20.          #10  code[3] = 0; code[2] = 1; code[1] = 1; code[0] = 1;
    21.          #10  code[3] = 1; code[2] = 0; code[1] = 0; code[0] = 0;
    22.          #10  code[3] = 1; code[2] = 0; code[1] = 0; code[0] = 1;
    23.          #10  code[3] = 1; code[2] = 0; code[1] = 1; code[0] = 0;
    24.          #10  code[3] = 1; code[2] = 0; code[1] = 1; code[0] = 1;
    25.          #10  code[3] = 1; code[2] = 1; code[1] = 0; code[0] = 0;
    26.          #10  code[3] = 1; code[2] = 1; code[1] = 0; code[0] = 1;
    27.          #10  code[3] = 1; code[2] = 1; code[1] = 1; code[0] = 0;
    28.          #10  code[3] = 1; code[2] = 1; code[1] = 1; code[0] = 1;
    29.          #10 $finish;
    30.       end
    31. initial
    32.      begin
    33.         $dumpfile ("binaryTo7Seg.dump");
    34.         $dumpvars (0, binaryTo7Seg_test);
    35.      end
    36.  
    37. endmodule
    Here is the result of the simulation
    Code ( (Unknown Language)):
    1.  
    2. 0  A = x B = x C = x D = x, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    3.                   10  A = 0 B = 0 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    4.                   20  A = 0 B = 0 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    5.                   30  A = 0 B = 0 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    6.                   40  A = 0 B = 0 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    7.                   50  A = 0 B = 1 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    8.                   60  A = 0 B = 1 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    9.                   70  A = 0 B = 1 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    10.                   80  A = 0 B = 1 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    11.                   90  A = 1 B = 0 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    12.                  100  A = 1 B = 0 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    13.                  110  A = 1 B = 0 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    14.                  120  A = 1 B = 0 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    15.                  130  A = 1 B = 1 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    16.                  140  A = 1 B = 1 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    17.                  150  A = 1 B = 1 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    18.                  160  A = 1 B = 1 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
    19.  
    Is there something wrong with my testbench?
     
  2. MaxSmoke

    Active Member

    Oct 29, 2009
    35
    0
    Should the above test bench statements not be ...

    reg [3:0] code;
    wire [7:0] segment;

    No need for the input & output statements.

    Hope this is of help.
     
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