Verilog - Code Posted - Please Help !!

Discussion in 'Programmer's Corner' started by dash82, Oct 23, 2007.

  1. dash82

    Thread Starter New Member

    Oct 23, 2007
    1
    0
    Hi Everyone,

    I am new to Verilog. I am trying to code a 1/2 rate convolutional encoder (http://en.wikipedia.org/wiki/Convolutional_code) in Verilog. I have the written the code and the test bench for it.

    However, i am going wrong somewhere. Anyone's help would be greatly appreciated. Please try helping !!

    Verilog code:

    //1/2 rate convolutional code with 3 registers; polynomials being (1,1,1) & //(1,0,1)

    module omencoder(out1,out2,in1,clk);


    output out1, out2;
    input in1,clk;


    reg u0 = 1'b0 ,u1 = 1'b0 ,u2 = 1'b0 , temp_u0, temp_u1, temp_u2;


    always @(in1)

    begin

    temp_u0 <= u0;
    temp_u1 <= u1;
    temp_u2 <= u2;

    //I was facing a race condition. Hence tried to put delay statement.
    #2 assign u2 = temp_u1;
    $display("value of u2 = %b",u2);
    #4 assign u1 = temp_u0;
    $display("value of u1 = %b",u1);
    #6 assign u0 = in1;
    $display("value of u0 = %b",u0);

    end

    //using polynomials (1,1,1) & (1,0,1)

    xor (out1,u0,u1,u2);
    xor (out2,u0,u2);

    endmodule


    ----------------------------------

    Testbench:

    --------------------------------------
    module stimulus;
    reg clk;
    reg in1 = 1'b1;


    omencoder om1(out1,out2,in1,clk);

    initial
    begin

    clk = 1'b1;


    #50 in1= 1'b1;
    #100 in1= 1'b0;
    #150 in1= 1'b1;
    #200 in1= 1'b0;
    //the last 2 input bits are used to flush the registers.
    #250 in1= 1'b0;
    #300 in1= 1'b0;
    #350 $finish;
    end

    initial
    $monitor("output bit 1 = %b, output bit 2 = %b", out1,out2);

    endmodule

    -----------------------------------------------------------------
     
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