# Verilog code help

Discussion in 'Programmer's Corner' started by dumindu89, Aug 15, 2012.

1. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
Help me to write the verilog code for a decade down counter with asynchronous parallel load and borrow. The operation is similar to the 74192 IC.

I can write the code for decade down counter.
But I have no idea how to implement the parallel load inputs and the borrow output.

Please help me to write the complete verilog code for this. Any suggestion? ( I am using Altera MAX II - EPM240T200C5N CPLD)

2. ### WBahn Moderator

Mar 31, 2012
18,087
4,917
Post the code that you can write and then clearly describe the behavior need for the remaining functions. We can proceed from there.

May 11, 2009
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4. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
Hello!
I decided to write the code using VHDL.

I found a VHDL code for a frequency divider (divided by 25) and I modified it to divide the frequency by 80. (I need a divided by 80 fixed divider too).

Code ( (Unknown Language)):
1. library IEEE;
2. use IEEE.STD_LOGIC_1164.ALL;
3. use IEEE.STD_LOGIC_ARITH.ALL;
4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
5.
6. entity divby_80 is
7.     Port (
8.            clk             : in  std_logic;
9.            reset: in std_logic;
10.            clk_out       : out std_logic
11.
12.     );
13.  end divby_80;
14.
15. architecture divby_80_a of divby_80 is
16. process(reset,clk)
17. begin
18. if (reset='0') then
19. count<=0;
20. clk_out<='0';
21. elsif rising_edge(clk) then
22. if (count=79) then
23. clk_out<=NOT(clk_out);
24. count<=0;
25. else
26. count<=count+1;
27. end if;
28. end if;
29. end process;
30. end divby_80_a;
I have two points in this code to understand.
why do we use "clk_out<=NOT(clk_out);" and why do we use a reset?
Once I finished the code for this fixed divider I can move to the programmable divider which is more complex.

I found this code too for a fixed frequency divider

Code ( (Unknown Language)):
1.  library IEEE;
2. use IEEE.STD_LOGIC_1164.ALL;
3. use IEEE.NUMERIC_STD.ALL;
4.
5. entity clk_gen is
6. port(   Clk : in std_logic;
7.         Clk_mod : out std_logic;
8.         divide_value : in integer
9.         );
10. end clk_gen;
11.
12. architecture Behavioral of clk_gen is
13.
14. signal counter,divide : integer := 80;
15.
16. begin
17.
18. divide <= divide_value;
19.
20. process(Clk)
21. begin
22.     if( rising_edge(Clk) ) then
23.         if(counter < divide/2-1) then
24.             counter <= counter + 1;
25.             Clk_mod <= '0';
26.         elsif(counter < divide-1) then
27.             counter <= counter + 1;
28.             Clk_mod <= '1';
29.         else
30.             Clk_mod <= '0';
31.             counter <= 0;
32.         end if;
33.     end if;
34. end process;
35.
36. end Behavioral;
37.

Last edited by a moderator: Sep 9, 2012
5. ### guitarguy12387 Active Member

Apr 10, 2008
359
12
For educational purposes, yeah it will probably work fine.

You're basically using an register (with a clock enable) to 'flip' the the output signal ( clk_out<=NOT(clk_out) when a certain count value is reached. The reset is used to provide a known initial state.

There's a few practical things that make this not ideal for many applications on an FPGA (i.e. asynchronous resets are generally bad practice on FPGAs, you should use specialized clock resources for deriving clocks instead of fabric, etc.), but for slow speeds and many scenarios, it will probably work okay.

6. ### WBahn Moderator

Mar 31, 2012
18,087
4,917
I don't think using asynchronous logic or gated clocks are safe at any speed in most FPGA designs. Being LUT based, logic signals in an FPGA are intrinsically glitchy.