verilog code for D flip flop

Discussion in 'Programmer's Corner' started by vead, Jan 2, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I have googled for D flip flop verilog code there are different type of code like synchronous set
    synchronous rest
    synchronous with positive edge clock
    now my question is that if I want to design flip Ic what code may be use I think i need to write code for synchronous set rest with positive edge clock I am not sure please anyone clear my doubt
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    It is a matter of what you, the designer, require. If you feel you need a set and reset, put it in, if not, leave it out.

    You need to figure out the specifications you need the device to have, then implement them...
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
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    when we design D flip flop in digital circuit we need to all like set , reset data clock, Q and Q0 now I can say this is complete D flip flop It work as flip flop
    but when we design in verilog I confused why we write code only for set or reset if we write verilog code only for set or reset does they work as flip flop?
     
  4. tshuck

    Well-Known Member

    Oct 18, 2012
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    A flip flop doesn't need any set or preset. It just needs to be an edge-triggered bistable element (stores 1 or 0 at a clock edge).
     
  5. t06afre

    AAC Fanatic!

    May 11, 2009
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  6. vead

    Thread Starter Active Member

    Nov 24, 2011
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    thats little bit different I explain what I am asking If I need D flip flop for counter
    so i need to write code for D flip flop but now I have choice
    synchronous set
    synchronous rest
    synchronous with positive edge clock

    which one should i used for counter
     
  7. t06afre

    AAC Fanatic!

    May 11, 2009
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    A counter may look someting like this in Verilog
    Code ( (Unknown Language)):
    1. module behav_counter( d, clk, clear, load, up_down, qd);
    2.  
    3. // Port Declaration
    4.  
    5. input   [7:0] d;
    6. input   clk;
    7. input   clear;
    8. input   load;
    9. input   up_down;
    10. output  [7:0] qd;
    11.  
    12. reg     [7:0] cnt;
    13.  
    14.  
    15. assign qd = cnt;
    16.  
    17.  
    18. always @ (posedge clk)
    19. begin
    20.     if (!clear)
    21.         cnt = 8'h00;
    22.     else if (load)
    23.         cnt = d;
    24.     else if (up_down)
    25.         cnt = cnt + 1;
    26.     else
    27.         cnt = cnt - 1;
    28. end
    29.  
    30. endmodule
    31.  
    At least this is the typical setup.
     
  8. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    That depends on what you want from the counter, doesn´t it. Without knowing that no one can tell you which one you should use.
     
  9. vead

    Thread Starter Active Member

    Nov 24, 2011
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    that's i am not asking I am asking about D flip flop I want to implement hardware of D flip flop (just paper work for my understanding) Now I have choice

    1) synchronous set
    2) synchronous rest
    3) synchronous set/reset with positive edge clock

    you meant that all are d flip flop I want to ask , can i get the above ICs of all D flip flop in market
     
  10. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    I think you can get a D with no sets or resets and a D with async set and reset, both in positive and negative edge triggered if I am not mistaken.
    Synchronous set and reset is more complicated to make, so I don´t think you can get them as single chips.
     
  11. t06afre

    AAC Fanatic!

    May 11, 2009
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    I am confused about this post. Your heading was verilog code for D flip flop. But now your request looks more like a request for a single chip with some D flip flop function.
     
    kubeek likes this.
  12. tshuck

    Well-Known Member

    Oct 18, 2012
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    There are plenty of ICs in the wild - just check out some of them (check out 7474, 74171, and 7479 in particular).

    Your Verilog code for a D flip-flop will, again, be whatever you feel you need. If you want to load it out with all possible features, go for it, in the end, if you don't need it, it's no big deal, just don't use it.

    What does it matter if you can get it in the market? You are designing this device yourself, it doesn't matter what is out there unless you want to convert the HDL to a schematic and hook the device up.

    I'm not sure why we had to tell you this. You are the designer for the application, you decide what is required to get the job done.
     
  13. vead

    Thread Starter Active Member

    Nov 24, 2011
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    ok, we can write verilog code for below

    1) synchronous set
    2) synchronous rest
    3) synchronous set/reset with positive edge clock

    can anyone explain what is difference between them
     
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