verilog case statement

Discussion in 'Embedded Systems and Microcontrollers' started by taimoortareen, Feb 22, 2014.

  1. taimoortareen

    Thread Starter New Member

    Feb 22, 2014
    1
    0
    hi ,
    i am facing a problem in verilog case statement .when i put inputs (00,01,10,11) at inputs 00 and 10 to cntrl1 and cntrl2, it outputs the value from in0.
    i use Xilinx software and my code is as follows :

    module multiplexer(out,in0,in1,in2,in3,cntrl1,cntrl2);

    input in0,in1,in2,in3,cntrl1,cntrl2;
    output out;
    reg out;

    always @(in0 or in1 or in2 or in3 or cntrl1 or cntrl2)

    case ({cntrl2,cntrl2})

    2'b00 : out = in0;
    2'b01 : out = in1;
    2'b10 : out = in2;
    2'b11 : out = in3;
    default : $display("Please check control bits");
    endcase

    endmodule
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Your case statement will only ever go to 00, or 11 - you've concatenated the same signal together...
     
  3. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Yeah, maybe you should put "case({cntrl1, cntrl2})...."
     
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