Verilog blocking vs non-blocking

Discussion in 'Embedded Systems and Microcontrollers' started by Shagas, Jul 31, 2014.

  1. Shagas

    Thread Starter Active Member

    May 13, 2013
    802
    74
    Hello

    Could someone elaborate on the following please?
    What would be the difference in functionality in the following two codes?
    (the only difference is the blocking vs non-blocking assignments)


    Code ( (Unknown Language)):
    1.  
    2. always @ (posedge clk) // counter
    3.                 begin
    4.                 if(switch == 1'b1) // switch is input
    5.                     begin
    6.                     led_d = 1'b1; // led_d is an led output
    7.                     end
    8.                
    9.                 if(led_d == 1'b1)
    10.                     begin
    11.                     counter = counter + 1'b1;
    12.                     end
    13.                
    14.                 if(counter > 26'd100000000)
    15.                     begin
    16.                     counter = 26'd0;
    17.                     led_d = 1'b0;
    18.                     end
    19.                
    20.                
    21.                 end
    Versus

    Code ( (Unknown Language)):
    1.  
    2. always @ (posedge clk) // counter
    3.                 begin
    4.                 if(switch == 1'b1) // switch is input
    5.                     begin
    6.                     led_d <= 1'b1; // led_d is an led output
    7.                     end
    8.                
    9.                 if(led_d == 1'b1)
    10.                     begin
    11.                     counter <= counter + 1'b1;
    12.                     end
    13.                
    14.                 if(counter > 26'd100000000)
    15.                     begin
    16.                     counter <= 26'd0;
    17.                     led_d <= 1'b0;
    18.                     end
    19.                
    20.                
    21.                 end
    22.  
    Q1)In the first version won't there be a danger that when the counter does go over that big number (3rd if statement) and led_d will be assigned to 1'b0 and if the switch is simultaneously pressed and the led_d will be assigned to 1'b1 . What would happen then? That's a conflict of drivers.

    Q2)Also if I used blocking assignments in those if statements then would execute sequentially right?

    Q3)Does it make sense to put a blocking and non-blocking assignment in an if statement? Won't they be executed synchronously anyway? (if it's just one bl and one non-bl)
     
    Last edited: Jul 31, 2014
  2. Shagas

    Thread Starter Active Member

    May 13, 2013
    802
    74
    Perhaps I can put it another way...
    Is it possible for me to synthesize a design in verilog (I'm using xilinx ise and Spartan 6)
    and load it onto the FPGA that would destroy the chip? Or would the synthesizer always prevent such a mistake from happening? I'm not talking about performing intense calculations that would generate alot of heat , I'm talking about physical synthesis error.
     
  3. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    I think the difference will be that one of those will begin counting right away when you toggle the switch, while the other will start a clock cycle later. But I may be wrong on this one, so best try simulating both and see what actually happens.

    Second thing: No you cannot make the chip destroy itself by writing some code (using the tools they provide). That would be a really bad design flaw. The only two things that I can think of, apart from thermal issues, are dv/dt (risetime) problems and thus SCR latchup which is covered by the manufacturing technology etc, and connecting two outputs together.

    If I remeber correctly there is a way to write code in verilog that connects two outputs together, but this still goes through a "strength" table which ultimately decides which of the outputs has priority, so in reality two simultaneous outputs will never happen.

    Last issue that I can brainstorm is a possibility that the binary file in the flash memory could be corrrupted, then unless the chip has some crc check the chip could get damaged.
     
  4. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    There should be no difference in the behavior between the two codings. All the signals will be sampled before any are updated (if your synthesizer works correctly)
    And, no you absolutely cannot destroy a chip by configuring with bad code.
     
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