I wrote this module using ModelSim/Verilog and it compiles and runs fine, but now I don't know how to write the testbench to go along with it in order to test it.
Here is the module that I wrote:
Here is what I have so far for the testbench:
I haven't written any testbenches so far, and I'm not really sure what goes in the test stimulus section. Thanks in advance for any guidance I might receive. The only thing that I do know about the test stimulus section is that a for loop is supposed to go in there to make implementation easier.
Here is the module that I wrote:
Rich (BB code):
module BCDecode(BCDinpt, segcntrl);
input [3:0] BCDinpt;
output reg[6:0] segcntrl;
always @(BCDinpt);
begin
case(BCDinpt)
0: segcntrl = 7'b1111110;
1: segcntrl = 7'b0110000;
2: segcntrl = 7'b1101101;
3: segcntrl = 7'b1111001;
4: segcntrl = 7'b0110011;
5: segcntrl = 7'b1011011;
6: segcntrl = 7'b1011111;
7: segcntrl = 7'b1110000;
8: segcntrl = 7'b1111111;
9: segcntrl = 7'b1111011;
default: segcntrl = 7'b0000001;
endcase
endmodule
Rich (BB code):
'timescale 1ns / 1ns
module test_BCD;
reg [3:0] BCDin;
wire [6:0] segout;
BCDecode BCDmodule (BCDin, segout);
initial //Clock generator
begin
BCDin = 4'b0000;
BCDin = 4'b0001;
BCDin = 4'b0010;
BCDin = 4'b0011;
BCDin = 4'b0100;
BCDin = 4'b0101;
BCDin = 4'b0110;
BCDin = 4'b0111;
BCDin = 4'b1000;
BCDin = 4'b1001;
end
initial //Test Stimulus
begin
end
initial
$monitor ($stime, ,BCDin, , segout);
endmodule