Verilog 7 segment BCD testbench help?

Discussion in 'Homework Help' started by jucd, Apr 18, 2011.

  1. jucd

    Thread Starter New Member

    Apr 18, 2011
    1
    0
    I wrote this module using ModelSim/Verilog and it compiles and runs fine, but now I don't know how to write the testbench to go along with it in order to test it.
    Here is the module that I wrote:
    Code ( (Unknown Language)):
    1.  
    2. module BCDecode(BCDinpt, segcntrl);
    3.   input [3:0] BCDinpt;
    4.   output reg[6:0] segcntrl;
    5.  
    6. always @(BCDinpt);
    7.   begin
    8.     case(BCDinpt)
    9.       0: segcntrl = 7'b1111110;
    10.       1: segcntrl = 7'b0110000;
    11.       2: segcntrl = 7'b1101101;
    12.       3: segcntrl = 7'b1111001;
    13.       4: segcntrl = 7'b0110011;
    14.       5: segcntrl = 7'b1011011;
    15.       6: segcntrl = 7'b1011111;
    16.       7: segcntrl = 7'b1110000;
    17.       8: segcntrl = 7'b1111111;
    18.       9: segcntrl = 7'b1111011;
    19.       default: segcntrl = 7'b0000001;
    20.     endcase
    21. endmodule
    22.  
    Here is what I have so far for the testbench:
    Code ( (Unknown Language)):
    1.  
    2. 'timescale 1ns / 1ns
    3. module test_BCD;
    4.   reg [3:0] BCDin;
    5.   wire [6:0] segout;
    6.  
    7.   BCDecode BCDmodule (BCDin, segout);
    8.   initial //Clock generator
    9.     begin
    10.       BCDin = 4'b0000;
    11.       BCDin = 4'b0001;
    12.       BCDin = 4'b0010;
    13.       BCDin = 4'b0011;
    14.       BCDin = 4'b0100;
    15.       BCDin = 4'b0101;
    16.       BCDin = 4'b0110;
    17.       BCDin = 4'b0111;
    18.       BCDin = 4'b1000;
    19.       BCDin = 4'b1001;
    20.     end
    21.    
    22.   initial //Test Stimulus
    23.     begin
    24.      
    25.     end
    26.  
    27.   initial
    28.   $monitor ($stime, ,BCDin, , segout);
    29. endmodule  
    30.  
    I haven't written any testbenches so far, and I'm not really sure what goes in the test stimulus section. Thanks in advance for any guidance I might receive. The only thing that I do know about the test stimulus section is that a for loop is supposed to go in there to make implementation easier.
     
  2. guitarguy12387

    Active Member

    Apr 10, 2008
    359
    12
    First pass, it looks not too bad to me. Though I am not sure you're allowed to have multiple initial blocks...

    Use the initial blocks for just that... initialization!

    You can do this two ways. Since your code is simple and the test cases can be enumerated easily, you could do everything in the inital block, as you have. But note that you should use delays! Otherwise your input value will change instantaneously.

    Just add #20 for example behind each of those assignments.

    Otherwise, you could use the initial block properly and just initialize the inputs to zero. Then use an always block to generate your input signals.

    If you spend a few min on google reading some tutorials, you will understand better
     
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