I'm mocking up a basic 555 timer circuit so as to understand the fundamentals of the IC. The schematic I'm using suggests placing a capacitor across the power terminals in order to "smooth out" the voltage. Is this to protect the IC from voltage spikes? But if the power source is VDC doesn't that mean the current is stable? Or is this a precautionary measure taken on all circuits that incorporate IC(s)? Thank you.

 

I'm mocking up a basic 555 timer circuit so as to understand the fundamentals of the IC. The schematic I'm using suggests placing a capacitor across the power terminals in order to "smooth out" the voltage. Is this to protect the IC from voltage spikes? But if the power source is VDC doesn't that mean the current is stable? Or is this a precautionary measure taken on all circuits that incorporate IC(s)? Thank you.

This might shed some light on the subject:

http://forum.allaboutcircuits.com/threads/decoupling-or-bypass-capacitors-why.45583/

 

The capacitor is to store energy for the 555 when it switches. It is a "dirty" switcher, and puts a big transient back into the supply leads. Same reason you put a bypass cap on every 7400 series logic chip.

 

This might shed some light on the subject:

http://forum.allaboutcircuits.com/threads/decoupling-or-bypass-capacitors-why.45583/

The important linked page was gone - Capacitor Design Tips for PCB.

Here is another -- Design Tips: PCB Decoupling Capacitor.

 

The problem is that the leads/wires from the power supply to a circuit component have resistance and inductance that can cause a significant drop in voltage for a high-frequency/fast-risetime transient current.
A capacitor to ground near the source of the transient (in this case the 555) provides a low impedance to these high frequency currents and effectively reduces the voltage drop from the transient to a tolerable level.
Otherwise this transient voltage spike may be enough to cause a glitch in normal circuit operation.

 

I'm mocking up a basic 555 timer circuit so as to understand the fundamentals of the IC. The schematic I'm using suggests placing a capacitor across the power terminals in order to "smooth out" the voltage. Is this to protect the IC from voltage spikes? But if the power source is VDC doesn't that mean the current is stable? Or is this a precautionary measure taken on all circuits that incorporate IC(s)? Thank you.

Once I built a boost SMPSU that boosted its own Vcc, the idea being that it could start up on low, but rested battery and continue running as the terminal voltage sags. The whole circuit was fed via the flyback inductor with the flyback rectifier and filter electrolytic isolating the 555 from the drain of the MOSFET it was driving.

Running from 4x AA Ni-Cd cells I measured Vcc and found it was around 30V - then I went running for the data sheet.

Data sheets from several manufacturers gave ABSmax Vcc as 16 or 18V - the part on the board had the Hitachi brand on it.

 

The important linked page was gone - Capacitor Design Tips for PCB.

Here is another -- Design Tips: PCB Decoupling Capacitor.

Thanks Scott! I'm really enjoying the "Design Tips" article. So, if I understand the gist of the article the actual location and the geometry of the cap determine the degree of inductance in the circuit, right? And by reducing the geographical area (minimizing the PCB's plane surface) we are effectively minimizing the inductance. Does this follow? Now, the capacitor counteracts any emerging inductance thus, relieving the circuit of any unwanted AC distortion. And the cap minimizes circuit inductance by providing an electrical plate for the current to amass. So, the cap is acting like a "stop-valve" (electrical regulator). I don't quite understand how the cap minimizes the voltage drop. In my basic understanding I would think running power directly to the 555 timer, without any passive or active components, that there would be less effective impedance between those point versus the inclusion of a capacitor. I'm confused here Scott. Ohhh...Is it because the cap can amass a significant amount of voltage on its plates, and then discharge the necessary current to operate the IC, without sacrificing the chip's voltage demands? Perhaps my confusion revolves around understanding the fundamentals of cap operation. Thank you

 

The problem is that the leads/wires from the power supply to a circuit component have resistance and inductance that can cause a significant drop in voltage for a high-frequency/fast-risetime transient current.
A capacitor to ground near the source of the transient (in this case the 555) provides a low impedance to these high frequency currents and effectively reduces the voltage drop from the transient to a tolerable level.
Otherwise this transient voltage spike may be enough to cause a glitch in normal circuit operation.

Thank you "crutschow". Great explanation. If I understand you correctly, the moral of the "electrical" story is to make sure there's sufficient (and steady) voltage available for the 555, otherwise, one risks under powering the chip thus, sacrificing its performance. Am I in the ballpark here?

 

Thank you "crutschow". Great explanation. If I understand you correctly, the moral of the "electrical" story is to make sure there's sufficient (and steady) voltage available for the 555, otherwise, one risks under powering the chip thus, sacrificing its performance. Am I in the ballpark here?

It's not under-powering the chip that's the problem. It's that, if ICs are not decoupled with local capacitors from power to ground, then there is the risk of the circuit not operating properly such as false triggering or otherwise misbehaving for no apparent reason, all due to voltage spikes on the power line.

 

It's not under-powering the chip that's the problem. It's that, if ICs are not decoupled with local capacitors from power to ground, then there is the risk of the circuit not operating properly such as false triggering or otherwise misbehaving for no apparent reason, all due to voltage spikes on the power line.

And if there are other chips wired in parallel with the 555, the glitches on the power lines created when the 555 switches can upset the other chips...

 

Thanks Scott! I'm really enjoying the "Design Tips" article. So, if I understand the gist of the article the actual location and the geometry of the cap determine the degree of inductance in the circuit, right?

So, the double layer pcb like to design as one side is +V and another side is GND, that is narrow the distance, and two sides also became a big capacitor.

And by reducing the geographical area (minimizing the PCB's plane surface) we are effectively minimizing the inductance. Does this follow?

How a pcb layout will effecting the inductance, you can google : pcb antenna.

Now, the capacitor counteracts any emerging inductance thus, relieving the circuit of any unwanted AC distortion. And the cap minimizes circuit inductance by providing an electrical plate for the current to amass. So, the cap is acting like a "stop-valve" (electrical regulator). I don't quite understand how the cap minimizes the voltage drop. In my basic understanding I would think running power directly to the 555 timer, without any passive or active components, that there would be less effective impedance between those point versus the inclusion of a capacitor.

The first is that the input voltage and current must be enough to offer the load and a big capacitor as a big battery, normally the capacitor is charging, when the load draw some more current then the big capacitor will be discharge to the load to keep the voltage in a stable status, so the capacitor must be big enough.

I'm confused here Scott. Ohhh...Is it because the cap can amass a significant amount of voltage on its plates, and then discharge the necessary current to operate the IC, without sacrificing the chip's voltage demands?
Perhaps my confusion revolves around understanding the fundamentals of cap operation.
Thank you

You could treat the capacitor as a water pipe or bucket, and the pulse width of frequency as balls, the big balls and small balls, you will more easy to get to know it, when we put the cap in different place of circuit then it has different purpose, and different capacitance has different frequency to pass through, the small decoupling capacitor as 0.1uf or 0.01 uf are suit for the small pulse as high frequency to pass through, the big capacitor as 220 uf, 330 uf, 1000 uf, 2200 uf, they are suit for the bigger pulse as the low frequency to pass through.

So, here you can easily to memory them as small capacitors for small pulse that it was high frequency(F=1/T), big capacitors for bigger pulse that it was low frequency(F=1/T), also the T=1/F.

 

Thanks Scott! I'm really enjoying the "Design Tips" article. So, if I understand the gist of the article the actual location and the geometry of the cap determine the degree of inductance in the circuit, right? And by reducing the geographical area (minimizing the PCB's plane surface) we are effectively minimizing the inductance. Does this follow? Now, the capacitor counteracts any emerging inductance thus, relieving the circuit of any unwanted AC distortion. And the cap minimizes circuit inductance

"here comes the bride - all fat and wide" (old nursery rhyme) - make the tracks short and wide where you can, it isn't practical with most tracks in a design, so concentrate first of all on power rails.

Some capacitors are better than others, but they all have their uses. Electrolytics have spiral wound foil plates which introduces some parasitic inductance, but they're good for bulk capacitance in a small size. Normally you'd put a non-electrolytic in parallel with an electrolytic to shunt the unwanted inductance. With a board full of TTL. you'd have a 0.1uF disc ceramic close to the supply pins of every chip, on less noisy circuits you could possibly get away with only bypassing the electrolytics - but feel free to use something bigger. like 0.22 or 0.47uF. If you're doing RF work, its often advisable to have 2 or more capacitors shunting the electrolytic, you might for instance have a 0.1uF and a 10nF.