Hi all,
I'm trying to get to grips with this VHDL language. As part of that I'm following some exercises, one of which asks me to write some VHDL code to perform a 4-bit shift register operation (serial in, parallel out).
So, I had a very obvious idea in mind for this that I knew would work, but I decided to do some googling to see if there were any better solutions that I could try. I found reference to the use of the concatenation operator for shift register operation. It goes something like this:
I tried this technique in my own program (in fact the above is my own use of the technique) and it works. The only question I have now is; why does it work?!
I understand that concatenation is the act of joining two variables together. I have experience of this with strings in the C language.
So, I understand how a bit on the Serial_In can be added on to the 4-bit Parallel_Out signal. What I don't understand, is how the shifting works. I can see that it has something to do with operating on the Parallel_Out signal using "3 downto 1" instead of "3 downto 0", so the right-most bit is not part of the concatenation, but I can't quite grasp why this means it would be shifted?
Can anyone advise?
Thanks very much,
Brian
I'm trying to get to grips with this VHDL language. As part of that I'm following some exercises, one of which asks me to write some VHDL code to perform a 4-bit shift register operation (serial in, parallel out).
So, I had a very obvious idea in mind for this that I knew would work, but I decided to do some googling to see if there were any better solutions that I could try. I found reference to the use of the concatenation operator for shift register operation. It goes something like this:
Rich (BB code):
elsif (Man_Clock'event and Man_Clock = '1') then -- rising edge triggered
Parallel_Out <= Serial_In & Parallel_Out (3 downto 1);
I understand that concatenation is the act of joining two variables together. I have experience of this with strings in the C language.
So, I understand how a bit on the Serial_In can be added on to the 4-bit Parallel_Out signal. What I don't understand, is how the shifting works. I can see that it has something to do with operating on the Parallel_Out signal using "3 downto 1" instead of "3 downto 0", so the right-most bit is not part of the concatenation, but I can't quite grasp why this means it would be shifted?
Can anyone advise?
Thanks very much,
Brian