Hello everyone,

Please help! Urgent.

I am having some serious issue trying to use a single JK flip flop to build a frequency divider (divide by 2). Somehow my output "Q" either does not toggle at all or toggles at the wrong frequency. Or, the output just doesn't make sense.

The JK flip flop I use looks like the following:

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I also attached the circuit picture.

It is a 4 NAND gates JK FF. I tie both J and K node to VDD, and the CLK is my input. According to many textbook or on-line resources, the output should toggle at half of the CLK frequency. I am building this circuit in Cadence for my company...

I run the design in Cadence analog design environment but the output just doesn't toggle correctly. The 3 inputs NAND gates are CMOS NAND gate...3 parallel PMOS pull-up and 3 series NMOS pull-down. The 2 input NAND gate uses 2 parallel PMOS pull-up and 2 series NMOS pull-down. All 4 NAND gates use the same sizing, meaning all PMOS are same size and all NMOS are same size.

It is driving me crazy, I've worked on this the whole day. I am now doubting this topology even works. It looks like it is difficult to maintain good oscillation and the feedback usually can destroy the way the signal toggles. It doesn't look like an edge trigger FF either. I think DFF would work much better, but has anyone done this before and worked? Specifically, use JK FF as divide by 2 block in the industry.

I cannot figure out the timing requirements for each gate, is the timing for the 4 NAND gate very very important?

Please help....>_<!

Thank you guys so much!

 

I was trying to study this on my own. This guy may be helpful.

 

Don't drive yourself crazy This doesn't seem to be a learning exercise so just use a different chip...cd4013...job done. http://www.doctronics.co.uk/4013.htm

 

Why are you building a JK flip-flop from NAND gates, rather than using an off-the-shelf one ?

 

@Alec_t I am building it in an integrated circuit along with many other gates and circuit building blocks. Everything needs to be integrated on a piece of silicon.

 

Your diagram is for a pulse-triggered JK flip-flop, not an edge-triggered one. To toggle, it needs a well-defined short clock pulse. To get the divider behavior I think you're looking for, you need a master-slave arrangement with many more NAND gates. Try looking at http://www.electronics-tutorials.ws/sequential/seq_2.html . Not the first circuit, which is basically yours, but the second.

Second tip: if you're doing this on an FPGA, try to use one of their existing D-flip flops as a divider if at all possible. Or if you're doing standard cell, then use one of the flip-flops provided. Something that you build yourself from gates may not perform well, and may not work at all if routed poorly. Every flip-flop has a race condition in it, and could be sabotaged by poor routing. Take it from this old IC designer.

 

@Roderick Young Hi Roderick you are correct. Thank you very much for your help!

I spent too much time tracing a pulse triggered JK FF, and got really confused. Many on-line resources says Q toggles at rising clock edge and confused me.

After I used master slave JK configuration the circuit worked.

 

Why are you building a JK flip-flop from NAND gates, rather than using an off-the-shelf one ?

Probably worth reminding the TS that J & K inputs have to be held logic 1 to toggle on the clock edge.

A D flip flop will also divide CP by 2 if you feed the not-Q output back to the D input.

 

Your diagram is for a pulse-triggered JK flip-flop, not an edge-triggered one. To toggle, it needs a well-defined short clock pulse. To get the divider behavior I think you're looking for, you need a master-slave arrangement with many more NAND gates. Try looking at http://www.electronics-tutorials.ws/sequential/seq_2.html . Not the first circuit, which is basically yours, but the second.

Second tip: if you're doing this on an FPGA, try to use one of their existing D-flip flops as a divider if at all possible. Or if you're doing standard cell, then use one of the flip-flops provided. Something that you build yourself from gates may not perform well, and may not work at all if routed poorly. Every flip-flop has a race condition in it, and could be sabotaged by poor routing. Take it from this old IC designer.

Roderick you just keep surprising me.