Unexpected Orcad simulation result

Discussion in 'General Electronics Chat' started by mentaaal, Apr 27, 2008.

  1. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    0
    Hey guys, I am writing up a report on a practical we did and am baffled by the result of this orcad simulation:

    I constructed a basic schematic of an asynchronous 4 bit counter using JK flip-flops. We were then asked to make the counter stop after it reaches "1111" . I used a NAND gate to take in all the Q outputs and output a 0 when they are all 1. This was going to go through an AND gate along with the clock into the clock in of the least significant flip flop in order to effectively remove the clock from the circuit when this state occurs. The teacher has even explained this kind of setup to us and in theory it makes perfect sence but i dont know why this simulation is not working. In the schematic attached i have left the output of the NAND gate floating and removed the AND gate as they were not working anyway and I am still strying to figure out why the output of the NAND gate is not working properly.

    Also could someone please tell me what the blue lines mean as opposed to the normal green output.

    Cheers!
     
  2. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    It would be easier to assist you if you would show us the circuit configuration that was not working.

    hgmjr
     
  3. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
    451
    0
    Ok hgmjr, here is the intended schematic as requested.
     
  4. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    It appears that in the process of inhibiting the clock, the disable signal is unintentionally clocking the first stage.

    What you may want to consider is making use of the J and/or K inputs to the first stage to disable the counter.

    hgmjr
     
  5. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    The problem is that the 7422 has open collector outputs.
    Either change it to a 7420 which has totem-pole outputs, or add a 470 to 1k Ohm pull-up resistor from the output of the 7422 to Vcc.

    The reason you're getting three blue lines is to show that the output is floating, rather than being a steady logic state.

    In the real world, the circuit would probably work if not clocked very fast. The input to the 7408 is an emitter, with 4K on the base to Vcc. However, with open-collector outputs, you really should provide your own pull-up resistors rather than assuming that something else will do it for you.
     
  6. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
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    0
    :) How do you remember all this stuff?

    Thanks!
     
  7. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    Within an arm's reach:
    "The TTL Data Book for Design Engineers, Second Edition" by Texas Instruments (c) 1976.
    It's a tad dog-eared, but very handy - plenty of miles left on it ;)
    The 54/7422 is briefly described on the top of page 5-11, the 54/7420 on the facing page 5-10, and the 54/7408 on page 5-8.
    The inputs and outputs of all three IC's are all described on pages 6-2 and 6-10.

    Much of the battle is just knowing where to look stuff up!

    While you can get by with using just downloaded datasheets, it really helps a great deal to have most of a logic family in one reference book. ICs are cross-referenced very well in this book, and I can very rapidly track things down; whether by function, speed, input/output - nearly any parameter. It's much harder to get by with individual datasheets; you have to remember too much, and do way too much rooting around to find what you need.

    And for lag time, I have only my fingers and brain to blame ;)
     
  8. mentaaal

    Thread Starter Senior Member

    Oct 17, 2005
    451
    0
    Brilliant! I guess things like this come with experience and not all theory! That book sounds great although i have not much need for something like that right now as i am only a lowly student ;-)
    Perhaps in third year when i go into work experience and have time to tinker i shall get one.
     
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