Understanding simple linear regulator

Discussion in 'General Electronics Chat' started by newbie217, Jun 14, 2011.

  1. newbie217

    Thread Starter Active Member

    Apr 12, 2009
    52
    0
    For this simple linear regulator:

    http://www.candlepowerforums.com/vb...-Simple-Power-MOSFET-Linear-Current-Regulator

    The description says that you want NMOS Q1 to operate entirely in the linear region. Since this circuit is designed to be a constant current source to a load, don't we want the transistor to operate in saturation? That is, a constant current irrespective of VDS variation.

    Or is the 'linear' description more to do w/ the fact that this circuit dissipates power (ala resistor)?
     
  2. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    5,448
    782
    There's no requirement for the current source control element to be in saturation - quite the opposite. Once you hit saturation you've lost the ability to further control the current.

    Perhaps your intended use of the term "saturation" is not the conventional one?
     
  3. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    Saturation in a MOSFET is the opposite of saturation in a BJT.
    In this circuit, the current starts to drop precipitously when Vds drops below about 0.65V (in simulation). Vds<0.65V is the linear region.
    So yes, you want the MOSFET to operate in the saturation region.
     
  4. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,386
    1,605
    It is not the mosfet being in saturation that determines the constant current. The current is determined by the drive off Q2, which is forming a closed loop control. This circuit is very similar to an op-amp constant current sink.

    BTW, when driving this off a standard PWM (just goes on/off, no tri-state) you can safely loose R4.
     
  5. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    True, but current regulation starts to fail when the MOSFET enters the linear region, because the gate voltage has to increase in order to maintain the drain current, which in turn reduces the NPN collector (and emitter) current, which drops the voltage across R2...
    You get the picture.
     
  6. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,386
    1,605
    When the voltage across R2 decreases the NPN collector current also decreases which increases the fet gate voltage which increases the voltage across R2.

    It's a control loop. Somewhere in there a stable point of current regulation exists, as the OddOne pointed out.
     
  7. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    In principle, you can get rid of R4 and R3. In practice. you might need to make them into an attenuator. Five volts of PWM drive might not be enough to allow feedback to set the gate voltage. In the simulation, the gate voltage was 4.85V with Q3 out of the circuit. In this case, 5V on the base of Q3 would cut it off, which is what you want. With a non-typical Q1, it might not be enough.
    If you make the PWM drive voltage too high, you can encounter Vbe breakdown, and the current will rise above the feedback value. An input attenuator might be required, as I believe the optimum PWM peak voltage is about 9 or 10V.
    A problem I see with this circuit is that the 1Meg resistor R1 makes the gate risetime so slow that the duty cycle is distorted fairly severely. At 1kHz, with an input duty cycle of 50%, the output duty cycle is 45%.
    If you make R1 100k, the output duty cycle goes to 49.4%, but the required headroom goes up by about 3V.
     
  8. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    I'm not disputing that. I'm just saying that Q1 needs to remain in saturation for good regulation to occur.
     
  9. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,386
    1,605
    Good lord, I completely missed that Q3 is a PNP and thus completely wrong choice for this circuit. Put a grounded emitter NPN there and all is fine; that is so obvious I "saw" that being there till the third time I looked at this piece of doo-doo.

    If you follow the link to the original indestructible article then that is a better circuit, at least there is a better (lower) choice for the gate pull-up resistor (though there he doesn't intend it for PWM operation). Yes 1 M will kill any high frequency response there, though it may work ok for on/off.

    Reading OldOne's post a bit closer is kinda amusing, he has about half his facts correct but still manages to mangle senseless conclusions from them. "Watt's law" indeed!

    However, the whole circuit is perhaps overkill. I had a product last year I needed a PWM controlled constant current sink for a LED and I did it in just 2 parts (and neither was an IC nor cost more then a dime).

    The circuit described is intended to work at 12V and .75A. If we make any reasonable assumption about a majority of the power goes to the load and not the fet, we can safely say Vds is 6 volts max. Id is the .75A.

    Would you please indicate where this would be on the following?

    [​IMG]

    I believe it to be in the lower left corner, part of the linear region. Saturation doesn't start to 15 or 20 V on this device. MOSFETS work quite happily in the linear region, and that's where I use them for the most part.
     
  10. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    At 0.75A, the gate voltage would have to be about 4.4V in the saturaation region. When Vds starts dropping below ≈2V (e.g., due to increasing load resistance), Vgs will have to increase. When Vds≈0.3V, Vgs≈5V. I suspect you are reading the axes incorrectly.
    I made my comments based on a simulation of the circuit. I used a model (subcircuit) of International Rectifier's IRF520. Run the sim before you get too committed to the circuit working well when the MOSFET is in the linear region.
    Active current sources/sinks with lots of feedback (op amp), and a reference voltage that is independent of output current, work fine with the MOSFET in the linear region. This circuit has a lot less loop gain, and the reference voltage (Vbe) is strongly affected by collector (≈emitter) current. When Vds is low (linear region), Vgs must be higher to maintain Ids. Vgs being higher causes Ic (≈Ie) to decrease, which causes Vbe to decrease.This causes the output current to drop.
    Like I said, don't take my word for it. Simulate it or build it, if that's what it takes.
     
    Last edited: Jun 14, 2011
Loading...