Understanding frequency synthesizers (jitter, PLL)

Discussion in 'General Electronics Chat' started by danielb33, Mar 11, 2015.

  1. danielb33

    Thread Starter Member

    Aug 20, 2012
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    I am working on a design for the University of Minnesota for increasing MRI scanner resolution. I have not had to use jitter attenuating devices in the past Apparently, jitter on clocks really affects ADC resolution when using a external clock (I am using the CS5560).

    I am considering using the part shown in the link below for jitter attenuation.
    http://www.digikey.com/product-detail/en/MK2058-01SILF/800-2262-ND/2019431

    I plan to use 16MHz crystal for the device.

    First off - I don't understand why ICLK is needed. What is this, why is it there, and how do I decide how to use it appropriately? It seems that this is basic knowledge that I should understand because a kindergarten explanation is not given. I cant even tell if ICLK1 and ICLK2 are needed.

    Second - I do not understand loop bandwidth and how this relates to my crystal frequency? For instance, page 4 shows how to set the loop bandwidth. I do not understand how this relates to my clock frequency? Could someone explain this?

    Thanks for the help.
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    If you do not understand the basic concept of a phase locked loop, there is very little point in trying to explain it to you in a forum post. I'm not trying to be negative or impugn your basic knowledge of electronics or anything else. It is not "kindergarten stuff" as your original post seems to imply. Let's have you read an introductory article and then we can return to your questions.

    Pick one of the following "top google hits"
    http://www.analog.com/media/en/training-seminars/tutorials/MT-086.pdf
    http://www.ieee-uffc.org/frequency-control/learning/pdf/Kroupa.pdf
    http://www.freescale.com/files/rf_if/doc/app_note/AN535.pdf
     
  3. danielb33

    Thread Starter Member

    Aug 20, 2012
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    Thanks for the input. I will read the items in your links today and get back to you.
     
  4. danielb33

    Thread Starter Member

    Aug 20, 2012
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    I looked into the articles - honestly a bit over my head. I have my current schematic for this part of the schematic attached. Everything makes sense except the ICLK1 and ICLK. Where should I generate these clocks from? Am I correct that if I set SEL0, SEL1, SEL2 to 1, and use a 13.5MHz crystal (recommended by manufacturer) my output will be 13.5MHz? I know I need to use ICLK1/2 but I just don't get what the function is. How does the crystal, ICLK relate together to produce the output? Just need concepts to help me use the part not necessarily the physics of how the part could be made. Thanks for the support!

    Below is a link to all technical documentation regarding this part from the manufacturer.
    http://www.idt.com/products/clocks-...058-01-communications-clock-jitter-attenuator
     
  5. Papabravo

    Expert

    Feb 24, 2006
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    If those papers were too much for you then I fear you will be unable to do, optimize, and maintain this design. That is just the way it is.

    ICLK1 and ICLK2 can be, but do not have to be, generated from the output clock. That is why the part is referred to as a Phase Locked Loop. A common way to do this is to divide the output clock by some integer. Look again at the choices for SEL[0:2] to get an idea of some divisors you might use. One reason for having two inputs is to increase the range over which the part can maintain lock. ICLK1 might be OUTPUT_CLOCK / 3072 and ICLK2 might be OUTPUT_CLK / 3071. You would of course need some logic to switch between the two clocks. The loop will adjust the output clock in a linear fashion when you change between ICLK1 and ICLK2.

    Your other question had to do with loop bandwidth. A small value of loop bandwidth means that rapid changes in the output divided down by the divisor will be ignored. A larger bandwidth will react to changes quicker but be more susceptible to noise.

    The datasheet says the part requires a "pullable" crystal. This is one that is specifically cut for this application and will change its frequency of operation when the load capacitance seen by the crystal inside the chip is changed. If you don't know how to tune a crystal so that its frequency is centered in the "pullable" range then your going to have a really really hard time making this work. It's no crime to admit that some designs are beyond you and that you need expert help.

    Last is the damping factor. In a 2nd order transfer function a damping factor of 1, also known as critical damping, means the step response will have no overshoot. It may take a long time for the error to be reduced to zero but at least the system response will not overshoot the desired setpoint.
     
  6. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    It sounds like you think the MK2058 is a clock generator. It isn't. You generate the clock with something else (usually an integrated crystal oscillator), then run that signal through the 2058 to clean it up. Your first post had a link to the 2058 datasheet. As it shows on page one and explains on page 2, ICLK1 and ICLK2 are the inputs to the device. You connect the clock signal you want to clean up to either one of these, and select it with the state of the ISEL control pin. This is a simple 2:1 multiplexer. The 2058 uses it's own crystal oscillator as part of the cleanup circuit.

    ak
     
  7. Papabravo

    Expert

    Feb 24, 2006
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    Notice the phrase I used:

    ICLK1 and ICLK2 can be, but do not have to be, generated from the output clock.

    If you generate ICLK1 or ICLK2 from the output clock then you have an obvious phase locked loop. If on the other hand you used externally generated sources for ICKL1 and ICLK2 then you are phase locking to an external source, but you don't necessarily have a closed loop. The loop in this case refers to how the phase error is derived. There is also a less obvious inner loop that looks at the phase error and adjusts the output by means of the charge pump which creates a voltage that controls the VCO
     
  8. Papabravo

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  9. BR-549

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    Sep 22, 2013
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  10. danielb33

    Thread Starter Member

    Aug 20, 2012
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    Papa - thanks for the detailed information. This is outside my electronics experience, but I really don't have choice but to figure it out. Your last comments helped a lot.

    As far as the pull able crystal - the manufacturer gives recommended PCB layout, specific crystal that can be used, and capacitor choice for given crystal and selections. I think that portion will work.

    That link did help - I think I am understanding the loop idea a bit more.

    IF my thinking is correct, I can set SEL0, SEL1, SEL2 to logic 1. Use a 13.5MHz crystal - and tie cLK (output) directly to ICLK1 since ICLK only needs to be 1*crystal frequency with this selection setting. Correct?
     
  11. Papabravo

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    Feb 24, 2006
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    It may be a workable solution, but since the output clock is equal in frequency to the input clock it may not be optimal for your application. I suggest you run the experiment since you don't seem to have the insight or the experience to grind through the math at this point. As I understand it you want to reduce the jitter in the output clock to a minimum and I think using a reference frequency that is the output divided by at least 128 will be beneficial. You can still use your 13.5 MHz crystal, run the output through a seven stage counter, and back to ICLK1 or ICLK2. The unused input should be grounded according to the datasheet.

    The whole purpose of using the divisor is to ignore short term random fluctuations in the output clock for the purposes of the phase comparator. If there is a long term drift of the output frequency you want to correct this in a timely fashion. The right divisor is a compromise between eliminating jitter and ensuring long term accuracy. Let us know how it works out for you.

    On a storage scope plot of the output clock you will know that you have success if you can superimpose a single period of the clock 128 times and "keep the eye open".
    http://en.wikipedia.org/wiki/Eye_pattern

    Ooops..I see your problem you don't get to have access to the crystal frequency if you select an internal divisor. Let me think on this some more.

    If you select a 27 MHz crystal and use a divisor of 2 that will give you a 13.5 MHz output that you can feed back to ICLK1 or ICLK2. That might offer some improvement over a 13.5 MHz crystal and a divisor of 1. The only other choice is to use a lower speed clock. You also realize that with these choices you have the widest bandwidth in the loop filter.
     
    Last edited: Mar 14, 2015
    danielb33 likes this.
  12. danielb33

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    Aug 20, 2012
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    Sorry for the late response - been out of town for a week. Thanks for the feedback papa - I will do that and let the forum know how it goes.
     
  13. danielb33

    Thread Starter Member

    Aug 20, 2012
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    So I found that the part above is not only not recommended for new design by the manufacturer but the cyrstals are almost impossible to get, many have gone obsolete. New part is needed.

    Is there a problem with using the ceramic CMOS oscillator below as the input to the ADC? It has <1ps jitter, the ADC has about 500ps. This is a decent improvment, and I only need 3KHz of the 50KHz bandwidth. The better the jitter the higher the sampling rate I can achieve.

    https://www.pericom.com/assets/Datasheets/FD_3-3V.pdf

    If this doesn't work I might go with the LTC6950. It is complicated but they provide design references (custom).

    Thoughts?
     
  14. Papabravo

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    Feb 24, 2006
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    I did not see the reference in the datasheet to 50 kHz. Is that the frequency stability in ppm?
     
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