Understanding Component Delay in Timing Diagrams

Discussion in 'Homework Help' started by v2rocketboy, Apr 1, 2011.

  1. v2rocketboy

    Thread Starter New Member

    Apr 1, 2011
    7
    0
    Hi all,

    I am doing a digital design course and we very quickly jumped over the concepts of timing diagrams and delay caused by logic components. I am really struggling with drawing diagrams for circuits with and, or, not and considering propagation delay etc


    I want to know if there is an easy approach to draw them, for example just a simple timing diagram of an and gate having a delay of one unit of time could really help, i have no idea what to do with this stuff.:(

    Any help would be great!;)
     
  2. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    Do you have any exercise in mind, to talk over it as an example? It would help a lot. Talking abstractly won't do you any good in my opinion.
     
  3. v2rocketboy

    Thread Starter New Member

    Apr 1, 2011
    7
    0
    Ah sorry, should have been more specific,

    I am asked to draw a timing diagram for the circuit, assuming no delay

    F(a,b,c) = a'b' + a'c + b'

    Now after that I am asked to draw this circuits timing diagram assuming all gates have a propagation delay of 1 unit of time.

    I understand the no delay one, but when it gets to drawing out delays I get really really confused. So I don't know how to approach it properly, we are suppose to use non straight lines to show change in logic ie (lines on a angle) like __/----\__

    Thanks for you reply btw.
     
  4. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    First of all, let's define the propagation delay. It is the time one gate needs to display the correct result, after its input has been changed. The time it takes to "refresh" in a manner of speech. If that is clear, let's proceed forward.

    Are you sure you are asked to draw inclined lines on the signal transitions? Has that been done explicitly? In that level of knowledge that you are displaying that would require the notions of rise time, logic effort and logic zones. I think I can safely assume that you were misled and you need to draw pseudo-inclined transitions, that will in fact have to effect on the circuit.

    Now, on to the solution. Can you be more specific about the gates of the circuit? For now, I will assume that you have to invert the inputs with an inverter, AND them with 2-input AND gates and OR them with a 3-input OR gate.
    The path of the signal will be NOT->AND->OR.

    Let's examine the signal a as an example: From the time it enters the circuit and goes into the NOT gate (let's call that time t), it takes one time unit to be inverted. Thus, the outcome of the NOT gate will be ready and visible on time t+T, where T is one time unit.
    After that, the signal a' will enter an AND gate and the its output will change at the time t+2T.
    Finally, it will enter the OR gate whose result will be updated at time t+3T.

    Check this visual example and come back with any questions: http://www.esacademic.com/pictures/eswiki/83/SR_FF_timing_diagram.png
    You can find many more in a Google image search for "timing diagram".
     
  5. v2rocketboy

    Thread Starter New Member

    Apr 1, 2011
    7
    0
    you've assumed the circuit right, with the inclines, should I be able to draw them as normal and just assume that one unit of time goes from the 50% on the rise to 50% on the fall part of the signal?
     
  6. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    I can't say I understood what you tried to ask me. Why don't you make an effort on drawing the timing diagram and we 'll comment on it. Once again I suggest you not to try to quantify the inclinations as far as time is concerned. Just make rough approximations.

    Your timing diagram should have the following rows: A,B,C (which will be permutated), A',B',A'B',A'C and A'B'+A'C+B'. 8 in total.
     
Loading...