Understanding and correcting this circuit's behavior

Discussion in 'General Electronics Chat' started by diddy02, Aug 5, 2010.

  1. diddy02

    Thread Starter Member

    Sep 26, 2008
    Hey all,

    I have a PCB that takes a serial (RS232) input and outputs dual 400Vpp sinusoidals at a phase offset of 90 degrees. To do this, a uC interprets the RS232 input which specifies frequency of the sinusoidal output and outputs a number to a DAC. Here's a rough idea of components/flow.

    RS232 -> uC -> DAC -> OpAmp -> VCO -> Sinusoidal Outp

    Unfortunately, the behavior of the uC -> DAC is not how I need it to be. Firstly, the uC output vs. RS232 input has an inverse relationship. If the data from RS232 specifies that a high frequency should be used, the DAC input is lower. For the highest frequency, uC output to the DAC would be 0000. As the requested frequency drops, DAC input increases. This behavior is fine, but I needed to specify it to illustrate the problem.

    When the uC receives new frequency information, I *think* that the uC clears its internal buffers/memory to load in the new info, and during this brief time, the 'requested frequency' parameter in the uC memory would be 0. Thus output to the DAC would be maxed out. This is a problem because during requested frequency changes, the sinusoidal pauses briefly. When frequency is updated at a high rate, the output is not usable at all. Ideally, the output should transition from one frequency to the other.

    Please see attachment1 for an illustration of what normally happens. Here I'm updating the frequency of the output at a rate of 150ms through RS232. The measured output is from the DAC.

    attachment 2 shows the desired behavior. I can't reprogram the uC or anything like that... any modifications would have to be straight on the PCB.

    I'd really appreciate any input!
  2. sage.radachowsky


    May 11, 2010
    Hi Diddy2

    First, it's a strange problem because you don't have access to the uC code.
    I am guessing that every time the uC receives a new input, it first resets the DAC and then sets the new value. That's what it looks like.

    Without changing the code, you could do a "peak meter" circuit that would rise quickly to the peak and then decay slowly from there. It would not be perfect, but it could follow the curve as you write for "desired output". It would not decay as fast even if you desired that.

    Do you at least have a schematic?