Understand a cpld schematic design

Discussion in 'General Electronics Chat' started by clementina_venture, Nov 10, 2010.

  1. clementina_venture

    Thread Starter New Member

    Nov 10, 2010
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    Hello,
    I have attached a schematic design of a cpld that I have to modify to enlarge the pulse width, this is "IMP" signal.

    Can you help me to understand this design and suggest me how to proceed?

    Thanks
     
  2. jpanhalt

    AAC Fanatic!

    Jan 18, 2008
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    How sophisticated do you want to be? How wide is the present pulse relative to the period?

    A very simple method to widen a pulse is to use a re-triggerable one-shot. An LM555 (or similar) will do. It is triggered by the pulse and outputs a wider pulse depending on the values chosen for its RC timer. So long as the 555 pulse ends before the next input pulse, it will re-trigger.

    John
     
  3. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Need more info on the logic in the clock block and the IMP output block. What logic is inside them?
     
  4. clementina_venture

    Thread Starter New Member

    Nov 10, 2010
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    0
    I need to modify the CPLD, that is of XILINX XC9500. Blocks Lx are comparators and FDC are flip flop ( I think!). The pulse is 0.5us large and I want a value of 2.5us or more.
    I can't use instead an LM555... unfortunately!!

    Any other informations?
     
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