UART with Vhdl

Discussion in 'Embedded Systems and Microcontrollers' started by medo45mtc, Dec 22, 2009.

  1. medo45mtc

    Thread Starter New Member

    Dec 22, 2009
    2
    0
    HI all, i try to communicate with the rs232 to test a system using an fpga chip and i wrote a vhdl code for the transmition part i think it is working but i cant adjust it with the hyperterminal , if any body knows how to adjust the hyperterminal or to coummunicate using matlab please tell me

    note:the baud rate for the code is 19200 with no parity bit and stop bit='1'

    entity Transmitter is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    tick,start : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR (7 downto 0);
    dout : out STD_LOGIC);
    end Transmitter;
    architecture Behavioral of Transmitter is
    type state is (s0,s1);
    signal prsnt_state,nxt_state:state;
    signal reg_prsnt,reg_nxt:std_logic_vector(8 downto 0);
    signal count_p,count_n:std_logic_vector(3 downto 0);
    signal tx_prsnt,tx_nxt:std_logic;
    begin
    process(clk,reset)
    begin
    if reset='1' then
    count_p<="0000";
    prsnt_state<=s0;
    tx_prsnt<='1';
    elsif rising_edge(clk) then
    tx_prsnt<=tx_nxt;
    reg_prsnt<=reg_nxt;
    count_p<=count_n;
    prsnt_state<=nxt_state;
    end if;
    end process;
    process(prsnt_state,tick,count_p,start)
    begin
    tx_nxt<=tx_prsnt;
    reg_nxt<=reg_prsnt;
    count_n<=count_p;
    nxt_state<=prsnt_state;
    case prsnt_state is
    when s0=>
    if start='1' then
    reg_nxt<=din &'0';
    nxt_state<=s1;
    end if;
    when s1=>
    if tick='1' then
    if count_p=9 then
    tx_nxt<='1';
    count_n<="0000";
    nxt_state<=s0;
    else
    tx_nxt<=reg_prsnt(0);
    reg_nxt<='0'& reg_prsnt(8 downto 1);
    count_n<=count_p+"0001";
    end if;
    end if;
    end case;
    end process;
    dout<=tx_prsnt;
    end Behavioral;
     
  2. whirtwisu

    New Member

    Dec 25, 2009
    1
    0
  3. Papabravo

    Expert

    Feb 24, 2006
    10,144
    1,790
    I'm not sure what adjusting it with the hyperterminal means. If I were you I would set the FPGA up to transmit a single observable charater at a fixed repetition rate. I would then verify the framing and the bit rate with an oscilliscope and or a logic analyzer. There are many freeware terminal emulators besides hyperterminal which is among the most useless of programs. To debug your receiver I'd create a file with several million copies of a single chatacter and send that file to the FPGA. There you can strip the framing and output the data on a parallel port.
     
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