DIGI book chapter 12 Shift Registers part 12.2.1
Serial-in/serial-out devices under the device labeled CD4517b dual 64-bit serial-in/ serial-out shift register
There is no CLB labeled in the graphic, only a CL8.
Serial-in/serial-out devices under the device labeled CD4517b dual 64-bit serial-in/ serial-out shift register
There is no CLB labeled in the graphic, only a CL8.
A CD4517b dual 64-bit shift register is shown above. Note the taps at the 16th, 32nd, and 48th stages. That means that shift registers of those lengths can be configured from one of the 64-bit shifters. Of course, the 64-bit shifters may be cascaded to yield an 80-bit, 96-bit, 112-bit, or 128-bit shift register. The clock CLA and CLB need to be paralleled when cascading the two shifters. WEB and WEB are grounded for normal shifting operations. The data inputs to the shift registers A and B are DA and DB respectively.
Suppose that we require a 16-bit shift register. Can this be configured with the CD4517b? How about a 64-shift register from the same part?
Above we show A CD4517b wired as a 16-bit shift register for section B. The clock for section B is CLB. The data is clocked in at CLB. And the data delayed by 16-clocks is picked of off Q16B. WEB , the write enable, is grounded.
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