Two stage CMOS op-amp design

Discussion in 'Homework Help' started by top0126, Dec 7, 2013.

  1. top0126

    Thread Starter New Member

    Dec 7, 2013
    1
    0
    The condition of Op-amp is like that
    OP Amp : Rin > 100K, Av > 10000, Ro < 100

    So, I made it through Two stage CMOS op-amp
    [​IMG]
    [​IMG]
    [​IMG]

    * Schematics Netlist *

    C_C1 Vout _N_7 1uF
    I_I1 _N_9 Vss DC 90uA
    M_M1 _N_8 Vn _N_6 _N_6 PMOS0P5 L=1U W=18U
    M_M2 _N_7 0 _N_6 _N_6 PMOS0P5 L=1U W=18U
    M_M3 _N_8 _N_8 Vss Vss NMOS0P5 L=1.0U W=5U
    M_M4 _N_7 _N_8 Vss Vss NMOS0P5 L=1.0U W=5U
    M_M5 _N_6 _N_9 Vdd Vdd PMOS0P5 L=1U W=18U
    M_M6 Vout _N_7 Vss Vss NMOS0P5 L=1.0U W=5U
    M_M7 Vout _N_9 Vdd Vdd PMOS0P5 L=1U W=18U
    M_M8 _N_9 _N_9 Vdd Vdd PMOS0P5 L=1U W=18U
    V_V? Vss 0 DC 15V
    V_Vsig Vn 0 pulse (0V 2.5v 10uSec 0.1nSec 0.1nSec 10uSec 20uSec)

    * Level-1 Model for the 0.5-um NMOS Transistor (Part NMOS0P5)
    * (created by Anas Hamoui & Olivier Trescases)
    .model NMOS0P5 NMOS(Level=1 VTO=0.7 GAMMA=0.5 PHI=0.8
    + LD=0.08E-06 WD=0 UO=460 LAMBDA=0.1 TOX=9.5E-9 PB=0.9 CJ=0.57E-3
    + CJSW=120E-12 MJ=0.5 MJSW=0.4 CGDO=0.4E-9 JS=10E-9 CGBO=0.38E-9
    + CGSO=0.4E-9)

    * Level-1 Model for the 0.5-um PMOS Transistor (Part PMOS0P5)
    * (created by Anas Hamoui & Olivier Trescases)
    .model PMOS0P5 PMOS(Level=1 VTO=-0.8 GAMMA=0.45 PHI=0.75
    + LD=0.09E-06 WD=0 UO=115 LAMBDA=0.2 TOX=9.5E-9 PB=0.9 CJ=0.93E-3
    + CJSW=170E-12 MJ=0.5 MJSW=0.35 CGDO=0.35E-9 JS=5E-9 CGBO=0.38E-9
    + CGSO=0.35E-9)


    .TRAN 1uSec 400uSec 0uSec
    *
    .control
    run
    plot Vout Vn
    .endc
    *
    .end

    So, Why didn't it operate ?
     
  2. absf

    Senior Member

    Dec 29, 2010
    1,490
    371
    I would check the polarity of the battery for VSS.

    Allen
     
  3. shteii01

    AAC Fanatic!

    Feb 19, 2010
    3,380
    494
    +1
    If I am reading it right, the Vss is wrong in the simulation.
     
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