TWO NMOS in series mean AND GATE? Then, this is also AND GATE??

Discussion in 'Homework Help' started by whitewar1004, Nov 4, 2007.

  1. whitewar1004

    Thread Starter New Member

    Dec 3, 2006
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    0
    The picture i attached, it also looks like two nmos connected in series except the fact that the inputs are kinda weird....
    F=(A*~(A))...this function will always output zero ....which makes no sense as a logic gate......
    so I believe that this is not an AND Gate?:(
    Well please correct me if i am wrong..

    Also, can I interpret that B, ~(B) as Vdd, and ground??:confused:
     
  2. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
    6
    That will indeed not work. Output will be zero.

    Its more customary to use transistors in series for an AND gate and in parallel for an OR gate. No inversion is required with the customary layouts. http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/trangate.html The examples are BJT, but N-channel FETs would work in the same way.
     
  3. whitewar1004

    Thread Starter New Member

    Dec 3, 2006
    4
    0
    the question asks what is F as a logic gate or something.....so I believe this thing should be doing something other than giving zero all the time..:D
     
  4. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
    6
    Having another look at it, it is indeed a gate!

    A * B' + A' * B

    Look familiar? One or the other high, but not both?
     
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