Hey, Im putting together a timed circuit. The issue is that I can no longer simulate the circuit without getting convergence issues. I have tried to help file but Im having troubles understanding it. Each time I made changes I would save the file ESM#. At ESM9 the file was simulating ok, then at ESM10 it stopped, I changed the ESM10 circuit to be exactly the same as ESM9 again and still get the convergence error, but the ESM9 file simulates fine.

Does anybody have any experience with this and could help with my issue. Here is the working ESM9 file and the not working ESM9-2 (ESM10) file in the .zip file in the attachments.

Thanks in advance

 

Yes, I have had similar experiences with an old Workbench program and I know of no solution other then to redraw the circuit. Apparently there is is subtle change in the circuit netlist which causes the non-convergence. If you compared the two netlists you might be able to determine what the difference is.