Two FSM Problems

Discussion in 'Homework Help' started by KillerZ123, Nov 25, 2010.

  1. KillerZ123

    Thread Starter New Member

    Nov 25, 2010
    7
    0
    The first problem has an input w and output z. z is 1 when the input w previous 4 values are either 1111 or 1010 overlapping patterns are allowed. Here is some test inputs and their outputs:

    w = 0101111010100111110
    z = 0000000100101000011

    I need to
    a) Show state table.
    b) Minimize to determine a non-redundant state table states.
    c) Write the VHDL code.

    a) From the outputs I can see that this is a moore fsm. I have the state table and diagram here:

    [​IMG]
    [​IMG]

    b) When I attempt to minimize this I don't find any redundant states:
    P1 = (ABCDEFGH)
    P2 = (ABCDFG)(EH)
    P3 = (ABCF)(G)(D)(E)(H)
    P4 = (A)(B)(C)(D)(E)(F)(G)(H)

    c)When I simulate my vhdl code using a functional simulation my machine acts like a mealy machine which I don't want and I am not sure why. I am using quartus to do my simulation. The states are assigned values instead of auto assigned values because I used them values to make a karnaugh maps to draw the FSM.

    VHDL:

    Code ( (Unknown Language)):
    1. LIBRARY ieee;
    2. USE ieee.std_logic_1164.all;
    3.  
    4. ENTITY mfsm IS
    5.     PORT(Clock, Resetn, w: IN STD_LOGIC;
    6.         z    :OUT STD_LOGIC);
    7. END mfsm;
    8.  
    9. ARCHITECTURE Behavior OF mfsm IS
    10.     SIGNAL y_present, y_next : STD_LOGIC_VECTOR(2 DOWNTO 0);
    11.     CONSTANT A : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
    12.     CONSTANT B : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
    13.     CONSTANT C : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
    14.     CONSTANT D : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
    15.     CONSTANT E : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
    16.     CONSTANT F : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
    17.     CONSTANT G : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
    18.     CONSTANT H : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
    19. BEGIN
    20.     PROCESS(w, y_present)
    21.     BEGIN
    22.         CASE y_present IS
    23.             WHEN A =>
    24.                 IF w = '0' THEN y_next <= A;
    25.                 ELSE y_next <= B;
    26.                 END IF;
    27.             WHEN B =>
    28.                 IF w = '0' THEN y_next <= F;
    29.                 ELSE y_next <= C;
    30.                 END IF;
    31.             WHEN C =>
    32.                 IF w = '0' THEN y_next <= F;
    33.                 ELSE y_next <= D;
    34.                 END IF;
    35.             WHEN D =>
    36.                 IF w = '0' THEN y_next <= F;
    37.                 ELSE y_next <= E;
    38.                 END IF;
    39.             WHEN E =>
    40.                 IF w = '0' THEN y_next <= F;
    41.                 ELSE y_next <= E;
    42.                 END IF;
    43.             WHEN F =>
    44.                 IF w = '0' THEN y_next <= A;
    45.                 ELSE y_next <= G;
    46.                 END IF;
    47.             WHEN G =>
    48.                 IF w = '0' THEN y_next <= H;
    49.                 ELSE y_next <= C;
    50.                 END IF;
    51.             WHEN H =>
    52.                 IF w = '0' THEN y_next <= A;
    53.                 ELSE y_next <= G;
    54.                 END IF;
    55.             WHEN OTHERS =>
    56.                 y_next <= A;
    57.         END CASE;
    58.     END PROCESS;    
    59.            
    60.     PROCESS(Clock, Resetn)
    61.     BEGIN
    62.         IF Resetn = '0' THEN
    63.             y_present <= A;
    64.         ELSIF(RISING_EDGE(Clock)) THEN
    65.             y_present <= y_next;
    66.         END IF;        
    67.     END PROCESS;
    68.    
    69.     PROCESS(y_present)
    70.     BEGIN
    71.         CASE y_present IS
    72.             WHEN E =>
    73.                 z <= '1';
    74.             WHEN H =>
    75.                 z <= '1';
    76.             WHEN OTHERS =>
    77.                 z <= '0';
    78.         END CASE;
    79.     END PROCESS;    
    80. END Behavior;
    Here is the sim wave form:

    [​IMG]

    The second question is similar to the first but in need to make a fsm that has three inputs w1, w2, w3 that if equal for any three consecutive cycles z will be 1. Here are some test inputs and their outputs:

    w1 = 0110111000110
    w2 = 1110101000101
    w3 = 0110100000110
    z = 0001100001100

    I need to:
    a) Show state table.
    b) Write vhdl code.

    a) From outputs this is a mealy fsm my state table and diagram are:

    [​IMG]
    [​IMG]
    To get x I made a circuit to see if w1, w2, w3 are equal (in vhdl code).

    b)My problem with this is my vhdl code seems to have a similar problem as the first question and I can't figure it out. I let the states be auto assigned this time.

    VHDL:

    Code ( (Unknown Language)):
    1. LIBRARY ieee;
    2. USE ieee.std_logic_1164.all;
    3.  
    4. ENTITY mealy IS
    5.     PORT(Clock, Resetn, w1, w2, w3 :IN STD_LOGIC;
    6.         z    :OUT STD_LOGIC);
    7. END mealy;
    8.  
    9. ARCHITECTURE Behavior OF mealy IS
    10.     TYPE State_type IS(A,B,C);
    11.     SIGNAL y: State_type;
    12.     SIGNAL x: STD_LOGIC;
    13. BEGIN
    14.     x <= ((w1 AND w2 AND w3) OR ((NOT w1) AND (NOT w2) AND (NOT w3)));
    15.     PROCESS(Resetn, Clock)
    16.     BEGIN
    17.         IF Resetn = '0' THEN
    18.             y <= A;
    19.         ELSIF(Clock'EVENT AND Clock = '1') THEN
    20.             CASE y IS
    21.                 WHEN A =>
    22.                     IF x = '0' THEN y <= A;
    23.                     ELSE y <= B;
    24.                     END IF;
    25.                 WHEN B =>
    26.                     IF x = '0' THEN y <= A;
    27.                     ELSE y <= C;
    28.                     END IF;
    29.                 WHEN C =>
    30.                     IF x = '0' THEN y <= A;
    31.                     ELSE y <= C;
    32.                     END IF;
    33.             END CASE;
    34.         END IF;
    35.     END PROCESS;
    36.    
    37.     PROCESS(y,x)
    38.     BEGIN
    39.         CASE y IS
    40.             WHEN A =>
    41.                 z <= '0';
    42.             WHEN B =>
    43.                 z <= '0';
    44.             WHEN C =>
    45.                 z <= x;
    46.         END CASE;
    47.     END PROCESS;
    48. END Behavior;
    This results in this sim output which seems to be making z = 1 at two not three:

    [​IMG]
     
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